- Tensilica Instruction Extension
Tensilica Instruciton Extension refers to the language that is used to extend the
Xtensaprocessor core instruction set. TIE in its syntax, is closer to the Hardware description language- Verilog. TIE allows the user to extend the functionality and increase the performance of the Xtensa processor cores by adding new instructions to the processor. TIE is also used to instantiate TIE Ports and TIE Queues in the Xtensa processor cores. TIE ports and TIE queues enable the design engineer to add designer defined input and output interfaces to the processor core.Using the TIE language and Xtensa Xplorer toolkit, the generation and verification of the instructions used to extend the processor ISA are automated. Such automation helps to reduce the hardware verification time that typically consumes a large percentage of the project duration of a typical hardware developed for the same functionality.
TIE was added by Tensilica to extend the instruction set of the Xtensa processors.
TIE code can be created in two ways. TIE can be:
#Manually written and attached to the required processor core.
#Automatically generated using Xtensa Xpress.
Manual coding is similar to
programmingusing other languages. Automatic generation of TIE code is done using Xtensa Xpress tool. This is done by first compiling & executing the code using the Xplorer and Xtensa Xpress tools. Xpress analyses the code that will be executed on the processor and generates additional TIE instructions for the processor core. These additional instructions will be automatically substituted when the C/C++ compiler generates the assembly code, preventing any manual intervention. This provides a complete user abstraction to the automatic TIE generation process.
Interface to C/C++
TIE extended instructions are called "operations" in TIE language. Since TIE compiler generates compiler intrinsics for each TIE operation, the TIE instructions can be invoked directly using the function call semantics of C language. The C compiler takes care of translating the TIE intrinsics into the appropriate instructions to be executed in the assembly code that is generated.
The TIE compiler is used to compile code written in TIE language. TIE compiler automates the generation of the designer defined hardware instructions additions to the processor core. TIE compilation produces the following outputs:
#A Modeling Environment that can be simulated using ISS
#A Compiler Toolchain for the Configured Processor Core that includes the TIE intrinsics to be used
#Hardware RTL Source Code for TIE and
EDAscripts for synthesis and Verification
TIE Testing & Verification
Once the code has been compiled using the TIE compiler, there are minimum two levels of verification & testing required to verify the functionality.
#Software Testing: Using the intrinsic interfaces of TIE operations from C/C++, the TIEs are first integrated with the C code that tests the required application functionality. After such integration, testing of the software running on the Xtensa core is performed by using the software simulator on PC (The Xtensa simulator on PC is called Instruction Set Simulator - ISS).
#Hardware Verification: The TIE compiler's output RTL and Netlists are given as input to various simulators like Modelsim. the required functionality of the TIE is verified by hardware simulation. Such verification requires a Hardware/Software co-simulation environment to be prepared, where the required software can be tested for its functionality.
XtensaThe configurable processor core
VerilogThe hardware description language
* TIE syntax highlight script for
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