SDRAM latency

SDRAM latency refers to the delays incurred when a computer tries to access data in SDRAM. SDRAM latency is often measured in memory bus clock cycles. Because a modern CPU is much faster than SDRAM, the CPU has to wait for a relatively long time for a memory access to complete before it can process the data. SDRAM latency contributes to total memory latency, which causes a significant bottleneck for system performance in modern computers.

DRAM access

SDRAM is notationally organized into a grid like pattern, with "rows", and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. The steps for the memory controller to access data in SDRAM follow in order:

# First, the SDRAM is in an idle state.
# The controller issues the "Active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles.
# After the delay, column address and either "Read" or "Write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). The read data isn't however available until a few clock cycles later, because the memory is pipelined.
# When an access is requested to another row, the current row has to be deactivated by issuing the "Precharge" command. The precharge command takes a few clock cycles before a new "Active" command can be issued.

SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):

;tCAS :The number of clock cycles needed to access a certain column of Data in SDRAM. CAS Latency, or simply CAS, is known as Column Address Strobe Latency, sometimes referred to as tCL.;tRCD (RAS to CAS Delay):The number of Clock cycles needed between a Row Address Strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. Stands for Row address to Column address Delay.;tRP (RAS Precharge):The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time.;tRAS:The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. Known as Active to Precharge Delay. Historically, tRAS was defined as the time needed to establish the necessary potential between a bitline pair within the memory array until it was safe to write back the data to the memory cells of origin after a (destructive) read. Pay attention to the word read here. Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four. Now imagine someone closes the book you are reading from in the middle of a sentence. And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers). Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. Along with those hassles comes the self-explanatory risk for data corruption.

Measurements

As with almost all latency issues, the lower the number, the better. RAM speeds are given by the four numbers above, in the format "tCAS-tRCD-tRP-tRAS". So, for example, latency values given as 2.5-3-3-8 would indicate tCAS=2.5, tRCD=3, tRP=3, tRAS=8. (Note that .5 values of latency (such as 2.5) are only possible in Double data rate RAM, where two parts of each clock cycle are used)

Most computer users don't need to worry about SDRAM latency, because the computer can handle the auto-adjustment to RAM timing based on the Serial Presence Detect (SPD) ROM inside the RAM packaging that defines the four timing values, decided by the RAM manufacturer. Although the SDRAM latency timing can be adjusted manually, using lower latency settings than the module's rating (overclocking) may cause a computer to crash or fail to boot.

See also

* Dynamic random access memory
* Memory latency

External links

* [http://www.amd.com/us-en/Processors/ComputingSolutions/0,,30_288_13265_13295%5E13335,00.html AMD's guide to memory latencies]