Digital Clock Manager


Digital Clock Manager

Digital Clock Manager is a function for manipulating clock signals by: [1]

  • Multiply and divide an incoming clock (DFS).
  • Recondition a clock to, for example, ensure 50% duty cycle.
  • Phase shift (DLL).
  • Eliminate clock skew.

See also

References

  1. ^ "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs". http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf.  070804 xilinx.com

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