Media Independent Interface

Media Independent Interface

The Media Independent Interface (MII) was originally defined as a standard interface used to connect a Fast Ethernet (i.e. 100 Mbit/s) MAC-block to a PHY chip.

The MII design has been extended to support reduced signals and increases speeds. Current variants are Reduced Media Independent Interface, Gigabit Media Independent Interface, Reduced Gigabit Media Independent Interface, Serial Gigabit Media Independent Interface and 10 Gigabit Media Independent Interface.

The equivalent of MII for 10 megabit Ethernet is the Attachment Unit Interface.

Contents

Media Independent Interface

MII connector on a Sun Ultra 1 Creator workstation

Being media independent means that different types of PHY devices for connecting to different media (i.e. Twisted pair copper, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. The MII bus (standardized by IEEE 802.3u) connects different types of PHYs (Physical Transceivers) to Media Access Controllers (MAC). Thus any MAC may be used with any PHY, independent of the network signal transmission media. The MII bus transfers data using 4-bit words (nibble) in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s speed.

The MII can be used to connect a MAC to an external PHY using a pluggable connector (shown in the figure (extreme right)), or direct to a PHY chip which is on the same printed circuit board. On a PC the CNR connector Type B carries MII bus interface signals.

The MDIO Serial Management Interface (SMI) (see MDIO) is used to transfer management information between MAC and PHY.

The standard MII features a small set of registers[1]:

  • Basic Mode Configuration (#0)
  • Status Word (#1)
  • PHY Identification (#2, #3)
  • Ability Advertisement (#4)
  • Link Partner Ability (#5)
  • Auto Negotiation Expansion (#6)

The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bitmask with the following meaning:

0x8000 Capable of 100baseT4
0x7800 Capable of 10/100 HD/FD (most common)
0x0040 Preamble suppression permitted
0x0020 Autonegotiation complete
0x0010 Remote fault
0x0008 Capable of Autonegotiation
0x0004 Link established
0x0002 Jabber detected
0x0001 Extended MII register exist.

A more detailed reference on registers exported by MII-compatible PHY's can be found looking at the Linux MII interface definition (include/linux/mii.h) [1]

In operation of data transmission, the transmit enable signal (TXEN) is asserted Active to indicate the start of a Ethernet frame, and is held active until the frame's transmission is completed. Simultaneously, the transmit clock signal (TXCLK) is set to Active for every new group of data bits (TXD0-TXD3). At 2.5 MHz for 10 Mbit/s mode and 25 MHz for 100 Mbit/s mode.

During reception the receive data valid signal (RXDV) goes active when the frame starts, and is held active throughout the frame duration. The clock signal (RXCLK) goes active for every new group of receive data bits (RXD0-RXD3). For the shortest possible frame size of 64 bytes, this means ~130 clocks. Any frame transferred begins with sync bits before the data payload. At powerup the PHY usually adapts to whatever it's connected to (Auto-negotiation) unless you alter settings via the MDIO interface.

Reduced Media Independent Interface

Reduced Media Independent Interface (RMII) is a standard that addresses the connection of Ethernet physical layer transceivers (PHY) to Ethernet switches or the MAC portion of an end-device's Ethernet interface. It reduces the number of signals/pins required for connecting to the PHY from 16 (for an MII-compliant interface) to between 6 and 10. RMII is capable of supporting 10 and 100 Mbit/s; gigabit interfaces need a wider interface.

An Ethernet interface normally consists of 4 major parts: The MAC (Media Access Controller), the PHY (PHYsical Interface or transceiver), the magnetics, and the connector. Connectors with integrated magnetics are available. The MAC handles the high level portions of the Ethernet protocol (framing, error detection, when to transmit, etc.) and the PHY handles the low level logic (4B/5B encoding/decoding, SERDES (serialization/deserialization), and NRZI encoding/decoding) and analog portions. RMII is one of the possible interfaces between the MAC and PHY; others include MII and SNI, with additional wider interfaces (including XAUI, GBIC, SFP, SFF, XFP, and XFI) for gigabit and faster Ethernet links.

One or more MAC interfaces may be on the same chip and in some cases the chip may have many other functions. One or more PHY interfaces may be on the same chip, particularly in Ethernet switches. Some MAC and PHY ICs support both MII and RMII. Usually, the MAC and PHY are on the same board for 10/100 Ethernet though for gigabit and higher pluggable PHY modules may be used to allow the use of different media including twisted pair and optical fiber. Older coaxial Ethernet interfaces sometimes used an AUI interface between the MAC and transceiver which was often an external box (thicknet required an external transceiver).

By comparison, the MII interface requires two additional data lines in each direction, RX_DV and CRS are separate rather than multiplexed, a separate TX_CLK and RX_CLK are used instead of a shared reference clock, and a collision signal is added for a total of 7 additional lines. The added pin count is more of a burden on microcontrollers with built in MAC, FPGA's, multitport switches or repeaters, and PC motherboard chipsets than it is for a separate single port Ethernet MAC which partially explains why the older MII standard was more wasteful of pins.

Signals

  • TXD0 Transmit data bit 0 (MAC to PHY) (transmitted first)
  • TXD1 Transmit data bit 1 (MAC to PHY)
  • TX_EN When high, clock data on TXD0 and TXD1 to the transmitter (MAC to PHY)
  • RXD0 Receive data bit 0 (PHY to MAC) (received first)
  • RXD1 Receive data bit 1 (PHY to MAC)
  • CRS_DV, Carrier Sense (CRS)/RX_Data Valid(RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. (PHY to MAC)
  • RX_ER Receive Error (optional on switches) (PHY to MAC)
  • REF_CLK Continuous 50 MHz Reference Clock (may be shared among interfaces). Reference clock may be an input on both devices or may be driven from MAC to PHY.
  • MDIO Management data I/O line (IIC/SMBus/TWI compatible) (bidirectional, open drain)
  • MDC Management data clock line (bidirectional but MAC to PHY in practice (though perhaps the PHY can pull down MDC to slow transfer), open drain). MDC and MDIO can in some cases be shared among multiple PHYs and with other devices.

On multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.

RMII requires a 50 MHz clock where MII requires a 25 MHz clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only. Ie it's not double pumped.

Limitations

In 10 Mbit/s mode, TXD0/TXD1/RXD0/RXD1 are sampled on every tenth clock cycle. The standard does a poor job of explaining the timing of signals in 10 Mbit/s mode. Apparently data on signal lines is supposed to remain valid for 10 clock cycles so it can be sampled on any clock edge during that interval. TX_EN probably remains asserted for the duration of the packet. It appears that 10 Mbit/s mode can be implemented by inserting a divide by 10 prescaler with pulse gate or separate clock enable line. It does not appear that the prescaler has to be reset to synchronize it with any particular event; instead the two prescalers (MAC and PHY) operate asynchronously with respect to each other.

There is no signal which defines whether the interface is in 10 or 100 Mbit/s mode but obviously both the MAC and the PHY need to agree. This is presumably handled by the MDIO/MDC interface though things might get interesting if the PHY and switch renegotiate the link speed at an unexpected time (perhaps after a cable was disconnected and reconnected). Future versions of the RMII standard might specify a way to transmit data over TXD0/TXD1/RXD0/RXD1 pins while TX_EN and CRS_DV are de-asserted.

The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC.

RMII has no COL signal. Instead the COL signal is recreated by a logical AND operation of CRS and TX_EN. This change means there is a slight modification of the definition of CRS. On MII, CRS is asserted for both Rx and Tx frames. But on RMII the CRS signal is only asserted for Rx frames. This has a few consequences: The two error conditions "no carrier" and "lost carrier" cannot be detected on RMII. And furthermore, it is difficult or impossible to support shared media such as Thinnet with RMII.

Signal levels

TTL signal levels are used for 5 V or 3.3 V logic. Input high threshold is 2.0 V and low is 0.8 V. The specification specifies that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer. 5 V tolerance is probably found primarily on older MII only devices. On the other hand, newer devices may support 2.5 V and 1.8 V logic. National.com doesn't make 5 V tolerant RMII PHYs. National DP83848: no 5 V. SMSC LAN8187: 1.8 V to 3.3 V, not 5 V tolerant. Intel LXT9781/LXT9761 8/6 port PHY: 5 V tolerant. Atmel AT91SAM7XC256 microcontroller: 5 V tolerant, AMD 79C875 4 port PHY: 5 V tolerant, FPGAs sufficient to implement MAC are usually not 5 V tolerant.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive (and thus slew rates) need to be as slow as possible (rise times from 1- to 5 ns) in order to permit this. Drivers should be able to drive 25 pF of capacitance which allows for PCB traces up to 0.30 meters. At least the standard says the signals need not be treated as transmission lines. However, at 1 ns edge rates a trace longer than about 2.7 cm (1ns/(5.9ns/m)*(3.7 m/0.0254 m)*(1/6)), transmission line effects could be a significant problem; at 5 ns, traces can be 5 times longer. The IEEE version of the related MII standard specifies 68 Ω trace impedance.[2] National recommends running 50 Ω traces with 33 Ω (adds to driver output impedance) series termination resistors for either MII or RMII mode to reduce reflections and suggests that traces be kept under 0.15 meters long and matched within 0.05 meters on length to minimize skew.[citation needed]

Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode [3]

Gigabit Media Independent Interface

Gigabit Media Independent Interface (GMII) is an interface between the Media Access Control (MAC) device and the physical layer (PHY). The interface defines speeds up to 1000 Mbit/s, implemented using an eight bit data interface clocked at 125 MHz, and is backwards compatible with the Media Independent Interface (MII) specification. It can also operate on fall-back speeds of 10/100 Mbit/s as per the MII specification.

Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check (CRC) checksum.

The GMII interface is defined in IEEE Standard 802.3, 2000 Edition [2]

Transmitter

  • GTXCLK - clock signal for gigabit TX.. signals (125 MHz)
  • TXCLK - clock signal for 10/100 Mbit signals
  • TXD[7..0] - data to be transmitted
  • TXEN - transmitter enable
  • TXER - transmitter error (used to corrupt a packet)

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100 Mb speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10/100 Mb the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.

Receiver

  • RXCLK - received clock signal (recovered from incoming received data)
  • RXD[7..0] - received data
  • RXDV - signifies data received is valid
  • RXER - signifies data received has errors
  • COL - Collision Detect (half-duplex connections only)
  • CS - Carrier Sense (half-duplex connections only)

Management

  • MDC - Management interface clock
  • MDIO - Management interface I/O bidirectional pin.

The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage (see "IEEE 802.3,2000-22.2.4 Management Functions"), while the others are device specific. These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode.

Reduced Gigabit Media Independent Interface

Reduced Gigabit Media Independent Interface (RGMII) specifies a particular interface between an Ethernet MAC and PHY.

RGMII uses half the number of data pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit/s operation, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RX_CTL, RXC, RXD[3:0], TX_CTL, TXC, TXD[3:0] (12 pins, as opposed to GMII's 24). Ie FrameStart-BitClock-Data.

Unlike GMII, the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10/100 Mbit/s operation and by the MAC at 1000 Mbit/s.

RGMII supports Ethernet speeds of:

[Mbit/s] [MHz] Bits/Clockcycle
10 2.5 4
100 25  4
1000 125  8

Serial Gigabit Media Independent Interface

The Serial Gigabit Media Independent Interface (SGMII) is a variant of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. It is used for Gigabit Ethernet (contrary to Ethernet 10/100 for MII).

It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin count serial 8B/10B coded interface (commonly referred to as a SerDes). To carry frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC, SGMII uses a differential pair for data signals and for clocking signals, with both being present in each direction (i.e., transmit and receive), giving 8 signal lines in total.

10 Gigabit Media Independent Interface

10 Gigabit Media Independent Interface (XGMII) is a standard defined in IEEE 802.3 for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board. It is composed from two 32-bits datapaths (Rx & Tx) and two 4-bits control flows (Rxc & Txc), operating at 156.25 MHz DDR (312.5 MT/s).

Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI.

See also

References

External links


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