- MOESI protocol
This is a full
cache coherencyprotocol that encompasses all of the possible states commonly used in other protocols. As discussed in AMD64 Architecture Programmer's Manual Vol 2 'System Programming' [ [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf AMD64 Architecture Programmer's Manual Vol 2 'System Programming'] ] , each cache lineis in one of five states:
;Modified: A cache line in the modified state holds the most recent, correct copy of the data. The copy in main memory is stale (incorrect), and no other processor holds a copy.
;Owned: A cache line in the owned state holds the most recent, correct copy of the data. The owned state is similar to the shared state in that other processors can hold a copy of the most recent, correct data. Unlike the shared state, however, the copy in main memory can be stale (incorrect). Only one processor can hold the data in the owned state—all other processors must hold the data in the shared state.
;Exclusive: A cache line in the exclusive state holds the most recent, correct copy of the data. The copy in main memory is also the most recent, correct copy of the data. No other processor holds a copy of the data.
;Shared: A cache line in the shared state holds the most recent, correct copy of the data. Other processors in the system may hold copies of the data in the shared state, as well. The copy in main memory is also the most recent, correct copy of the data, if no other processor holds it in owned state.
;Invalid: A cache line in the invalid state does not hold a valid copy of the data. Valid copies of the data might be either in main memory or another processor cache.
For any given pair of caches, the permitted states of a given cache line are as follows:(The order in which the states are normally listed serves only to make the acronym "MOESI" pronounceable.)
This protocol, a more elaborate version of the simpler
MESI protocol, avoids the need to write modifications back to main memorywhen another processor tries to read it. Instead, the Owned state allows a processor to supply the modified data directly to the other processor. This is beneficial when the communication latency and bandwidth between two CPUs is significantly better than to main memory. An example would be multi-core CPUs with per-core L2 caches.
If a processor wishes to write to an Owned cache line, it must notify the other processors that are sharing that cache line. Depending on the implementation it may simply tell them to invalidate their copies (moving its own copy to the Modified state), or it may tell them to update their copies with the new contents (leaving its own copy in the Owned state).
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