McASP


McASP

McASP is an acronym for Multichannel Audio Serial Port, a communication peripheral found in Texas Instruments family of digital signal processors (DSPs).
The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
The McASP consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. The McASP module also includes up to 16 serializers that can be individually enabled to either transmit or receive. In addition, all of the McASP pins can be configured as general-purpose input/output (GPIO) pins.

Contents

Features

Features of the McASP include:

  • Two independent clock generator modules for transmit and receive
    • Clocking flexibility allows the McASP to receive and transmit at different rates. For example, the McASP can receive data at 48 kHz but output up-sampled data at 96 kHz or 192 kHz.
  • Independent transmit and receive modules, each includes:
    • Programmable clock and frame sync generator
    • TDM streams from 2 to 32, and 384 time slots
    • Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits
    • Data formatter for bit manipulation
  • Individually assignable serial data pins (up to 16 pins)
  • Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC), Codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components.
  • Wide variety of I2S and similar bit-stream format
  • Integrated digital audio interface transmitter (DIT) supports:
    • S/PDIF, IEC60958-1, AES-3 formats
    • Up to 16 transmit pins
    • Enhanced channel status/user data RAM
  • 384-slot TDM with external digital audio interface receiver (DIR) device
    • For DIR reception, an external DIR receiver integrated circuit should be used with I2S output format and connected to the McASP receive section.
  • Extensive error checking and recovery
    • Transmit underruns and receiver overruns due to the system not meeting real-time requirements
    • Early or late frame sync in TDM mode
    • Out-of-range high-frequency master clock for both transmit and receive
    • External error signal coming into the AMUTEIN input
    • DMA error due to incorrect programming

Protocols

The McASP supports a wide variety of protocols.

  • Transmit section supports
    • Wide variety of I2S and similar bit-stream formats
    • TDM streams from 2 to 32 time slots
    • S/PDIF, IEC60958-1, AES-3 formats
  • Receive section supports
    • Wide variety of I2S and similar bit-stream formats
    • TDM streams from 2 to 32 time slots
    • TDM stream of 384 time slots specifically designed for easy interface to external digital interface receiver (DIR) device transmitting DIR frames to McASP using the I2S protocol (one time slot for each DIR subframe)

The transmit and receive sections may each be individually programmed to support the following options on the basic serial protocol:

  • Programmable clock and frame sync polarity (rising or falling edge): ACLKR/X, AHCLKR/X and AFSR/X
  • Slot length (number of bits per time slot): 8, 12, 16, 20, 24, 28, 32 bits supported
  • Word length (bits per word): 8, 12, 16, 20, 24, 28, 32 bits; always less than or equal to the time slot length
  • First-bit data delay: 0, 1, 2 bit clocks
  • Left/right alignment of word inside slot
  • Bit order: MSB first or LSB first
  • Bit mask/pad/rotate function
    • Automatically aligns data for DSP internally in either Q31 or integer formats
    • Automatically masks nonsignificant bits (sets to 0, 1, or extends value of another bit)

In DIT mode, additional features of the transmitter are:

  • Transmit-only mode- 384 time slots (subframe) per frame
  • Bi-phase encoded 3.3 V output
  • Support for consumer and professional applications
  • Channel status RAM (384 bits)
  • User data RAM (384 bits)
  • Separate valid bit (V) for subframe A, B

See also

References


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