Datapath

A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations. Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to regulating the interaction between the datapath and main memory.

The purpose of datapaths is to provide routes for data to travel between functional units.These datapaths can be joined together to make bigger datapaths using multiplexers. A Sign extension unit can also be used in conjunction when bigger sized words are needed.

Recently there have been research efforts into reconfigurable datapaths. These datapaths can be imprinted onto fabrics and can be changed at runtime. This concept could revolutionize CPU design and allow for more efficient processing.

Functional blocks of a datapath

The important functional blocks inside the processor can be listed as:-

• Instruction register(IR)
• Program Counter(PC)
• General purpose registers

There are also 2 registers inherent in the processor that facilitate the communication of the processor with the memory,or basically help in the memory operations of the register.They are:-

• Memory address register(MAR)
• Memory data register(MDR).
  

Single bus organization of datapath

Single bus organization

The first and foremost important interconnecting medium for all the registers inside the processor is the System bus. This bus is the processor bus and is not to be confused with the external bus that connects different memory chips and I/O devices to the processor.

This external bus is connected to the internal System bus via the MAR and the MDR registers.The data lines of the external bus are connected to MDR and the address lines of the external bus are connected to the MAR.The MDR is a bidirectional register implying that it can receive and send data to and from any one of the two internal or external buses.The MAR is a unidirectional register.It receives it's input from the internal bus and gives it's output to the external bus.

The number of general purpose registers can vary from one processor to another.Every processor has some special purpose registers.These are are used as a temporary storage medium by the processor.

The Arithmetic logic unit(ALU) is used for performing arithmetic and logic operations on the data contained in different registers.It is the heart of the microprocessor.The multiplexer is provided for selecting either the constant value 4 or the register X. The constant value 4 is selected when one instruction is completed and The Program Counter is to be incremented.{As told before :- (PC ← (PC)+4)}. The "instruction decoder and control logic" block decodes and carries out the instruction present in the IR register. The processor uses all these blocks together to carry out different primary operations such as :-

1. Inter Register data transfers
2. Arithmetic or Logical operations
3. Retrieving data from Memory
4. Writing data into the Memory

Examples

Let us consider addition as an Arithmetic operation and Retrieving data from memory in detail.

Example 1) Arithmetic addition :-contents of register reg1 and reg2 are added and the result is stored in reg3

Sequence of operations:-

1. reg1_out,X_in
2. reg2_out,choose X,ADDITION,Y_in
3. Y_out,reg3_in

The control signals written in one line are executed in the same clock cycle. all other signals remain untouched.So, in the first step the contents of register1 are written into the register X through the bus.In the second stage the content of register2 is placed onto the bus and the Multiplexer is made to choose input X as the contents of reg1 are stored in register X.The ALU then adds the contents in the register X and reg1 and stores the result of the addition in the special temporary register Y.In the final step the result strored in Y is sent over to the register reg3 over the internal processor bus.Only one register can output its data onto bus in one step.[Hence steps 2 and 3 cannot be combined].^[1]

Example 2) Retrieving data from memory To retrieve data from memory, the processor has to provide the address of the memory location where the required data is saved. The data stored at a particular required memory location can be either an instruction of a program or the operand of a particular executable instruction. The sequence of operations for the above operation is as follows:-

1. reg1_out,MAR_in,,READM
2. MDR_inEX,WMC
3. MDR_out,reg2_in,
   

Fetching a word from memory

A new control signal WMC has been introduced here. WMC stands for Wait for Memory operation to Complete. Generally the addressed device on the memory bus is slower than the microprocessor.Therefore,the microprocessor has to wait for the addressed device to complete its operation.This indication that the memory operation has been completed is given to the processor by the control signal WMC.

Also, as described above, the MDR is a bidirectional register i.e. it is connected to both the internal and external buses.Therefore the signal MDR has subscript inEX . The EX stands for the external bus.The signal implies that data is moved from the external memory bus into the MDR register.The remaining control signals are self-explanatory and can be understood easily as in Example 1 where MDR is the bidirectional Memory data register and MAR is the unidirectional Memory Address Register.

An entire instruction is executed

Now,let us put together the primary operations to see how a complete instruction is executed.

Consider for example the instruction

ADD (reg3),reg1.
This instruction adds the data stored at the location pointed to by the register3 to the contents of register 1.The sequence of control signals for the aforementioned complete instruction are as follows:-

1. PCount_out,MAR_in,READM,Choose4,ADDITION,Y_in
2. Y_out,PC_in,Y_in,WMC
3. MDR_out,IReg_in
4. reg3_out,MAR_in,READM
5. reg1_out,X_in,WMC
6. MDR_out,ChooseX,ADDITION,Y_in
7. Y_out,reg1_in,HALT

The first 3 steps written above are common to all the instructions of a microprocessor.These constitute the "Fetching of Instruction" Phase mentioned earlier.After the execution of the first three steps the instruction is loaded into the instruction register.the "instruction decoding and control circuitry" then decode the instruction and switch on all the control signals needed for steps 4 through 7.The steps 4 through 7 constitute the "Execution based on fetch instruction phase".

The content of register 3 is copied into the MAR register in step 4,which gives the address of the desired memory location and the READM instruction is executed.The contents of the other register 1 are transferred over the bus to the register X.As soon as the READM operation is completed the data at the desired memory location is made available in the MDR.The multiplexer is made to choose X over 4 .The contents of the two register are added in step 6 using the ADDITION instruction.The result of the addition is stored in the special register Y. Finally the value stored in Y is transferred to register1 over the bus in step 7.

The contents of the updated program counter are copied into the register X in step 2.Although there is no need to do this in the above program,the updated value of PC is generally stored in the register X in case of Branched Instructions to calculate the 'branch target address'

Multi-Bus Organizations of datapath

The Internal Organization of Processor discussed above was a single bus organization.It was discussed to get the basic idea.Practically,however,such single bus microprocessors are not feasible.They result in lengthy control signal sequences.Therefore,to cut down on the number of steps needed to execute an instruction a multi-bus organization is used.

Multiple Bus Organization

See also

• Finite state machine with datapath

References

1. ^ Computer Organization by Hamacher, Zaky, vranesic

• Chapter 7, "Logic and Computer Design Fundamentals", Mano and Kime, 2000, Prentice Hall