Intel 8008

Intel 8008

Infobox Computer Hardware Cpu
name = Intel 8008

caption = An Intel 8008 Microprocessor
produced-start = mid 1972
produced-end = 1983 [ [ CPU History - The CPU Museum - Life Cycle of the CPU ] ]
slowest = 0.5 | slow-unit = Mhz
fastest = 0.8 | fast-unit = Mhz
manuf1 = Intel
arch = pre x86
pack1 = 18 pin DIP
The Intel 8008 was an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. Originally known as the 1201, the chip was commissioned by Computer Terminal Corporation (CTC) to implement an instruction set designed for their Datapoint 2200 programmable terminal. As the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL based CPU instead. An agreement permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.


CTC formed in San Antonio in 1968 under the direction of Austin O. "Gus" Roche and Phil Ray, both NASA engineers. Roche, in particular, was primarily interested in producing a desktop computer. However, given the immaturity of the market, the company's business plan mentioned only a ASR-33 Teletype replacement, which shipped as the Datapoint 3300. The case, designed by John "Jack" Frassanito, was deliberately designed to fit in the same space as an IBM Selectric typewriter, and used a video screen shaped to be the same aspect ratio as the IBM 029 punch card terminal.Lamont Wood, [ "Forgotten PC history: The true origins of the personal computer"] , "Computerworld", 8 August 2008] Although commercially successful, the 3300 had ongoing heat problems due to the amount of circuitry packed into such a small space.

In order to address the heating and other issues, a re-design started that featured all of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, Roche turned to Intel, then primarily a vendor of memory chips. Roche met with Bob Noyce, who expressed concern with the concept; Frassanito recalls that "Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer." Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a $50,000 development contract in early 1970. Texas Instruments (TI) was also brought in as a second supplier.

TI was able to quickly make samples of the 1201 based on Intel drawings, but these proved to be buggy and were rejected. Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using discrete TTL instead of a single CPU. The new system was released as the Datapoint 2200 in the spring 1970, with their first sale to General Mills on 25 May 1970. CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Six months later, Seiko approached Intel expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler Intel 4004 used by Busicom in their business calculators. A small re-design followed, expanding from a 16-pin to 18-pin design, and the new 1210 was delivered to CTC in late 1971.

By that point CTC had once again moved on, this time to the Datapoint 2200 II, which was faster and included a hard drive. The 1201 was no longer powerful enough for the new model. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008, and put it in their catalog in April 1972 priced at $120. Intel's initial worries about their existing customer base leaving them proved unfounded, and the 8008 went on to be a commercially successful design. This was followed by the Intel 8080, and then the hugely successful Intel x86 family.


Implemented in 10 μm silicon-gate enhancement load PMOS, initial versions of the 8008 ran at 0.5 MHz, later increased in the 8008-1 to 0.8 MHz. Instructions took between 3 and 11 cycles: register-register loads and ALU operations took 5T (10μs at 0.5 MHz), register-memory 8T (16μs), while (taken) calls and jumps took 11 cycles (22μs). The 8008 was a little slower in terms of instructions per second (45,000 to 100,000) [] than the 4-bit Intel 4004 and Intel 4040, but the fact that the 8008 processed data eight bits at a time and could access significantly more RAM still gave it a significant speed advantage in most applications. The 8008 had 3,500 transistors [ [ Reichel-Orbital museum - CPU Collection] ] .

The subsequent Intel 8080 and 8085 CPUs were also heavily based on the same basic design; even the x86 architecture (originally a non-strict extension of the 8085) loosely resembles the original Datapoint 2200 design (every instruction of the 8008's instruction set has a direct equivalent in the 8080's larger instruction set and Intel Core 2's even larger instruction set, although the opcode values are different in all three).

The chip (limited by its 18 pin DIP packaging) had a single 8-bit bus and required a significant amount of external support logic. For example, the 14-bit address, which could access "16 K x 8 bits of memory"cite web|url= MCS-8 User Manual|title=MCS-8 Users Manual|format=pdf] , needed to be latched by some of this logic into an external Memory Address Register (MAR). The 8008 could access 8 input ports and 24 output ports.

For controller and CRT terminal use this was an acceptable design, but it was too difficult to use for most other tasks. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.

The 8008 family is also referred to as the "MCS-8".


*CTC ("Instruction set and architecture"): Victor Poor and Harry Pyle.
*Intel ("Implementation in silicon"):
** Marcian "Ted" Hoff and Stan Mazor and Larry Potter (IBM Chief Scientist of IBM) proposed a single-chip implementation of the CTC architecture, using RAM register memory rather than shift register memory, and also added a few instructions and interrupt facility
** Federico Faggin become leader of the project from January 1971, after it had been suspended -without progress- for about 7 months, until its successful completion in April 1972
** Hal Feeney project engineer did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology Faggin originally developed for the Intel 4004 microprocessor and utilizing the circuits of the 4004.

External links

* [ MCS-8 User Manual] with 8008 data sheet (1972)
* [ Computer World] Forgotten PC history: The true origins of the personal computer
* [ The Intel 8008 support page] inofficial


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