Double patterning


Double patterning

Double patterning is a class of technologies developed for photolithography to enhance the feature density. For the semiconductor industry, double patterning is the only lithography technique to be used for the 32 nm and 22 nm half-pitch nodes in 2008-2009 and 2011-2012, respectively, using tools already available today.

There are several types of double patterning.

Double exposure

Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks. [ See for example, US Patent 5308741. ] This technique is commonly used for patterns in the same layer which look very different or have incompatible densities or pitches. In one important case, the two exposures may each consist of lines which are oriented in one or the other of two usually perpendicular directions. This allows the decomposition of two-dimensional patterns into two one-dimensional patterns which are easier to print. This is the basis of DDL technology from Brion Technologies, a subsidiary of ASML. [ [http://www.semiconductor.net/article/CA6483003.html Brion implements ASML' DDL Technology] ] The sum of the exposures cannot improve the minimum resolution limit unless the photoresist response is not a simple addition of the two exposures. The double exposure technique allows manufacturability of minimum pitch features in a layout that may contain a variety of features. The 65 nm node saw the introduction of alternating phase-shift masks in manufacturing. [ A. Tritchkov, S. Jeong, and C. Kenyon, "Lithography Enabling for the 65 nm node gate layer patterning with Alternating PSM," Proc. SPIE vol. 5754, pp.215-225 (2005). ] This technology is typically a double exposure approach. As long as double exposure can be used effectively and is kept within alignment tolerances, it is the preferred patterning approach since it does not require additional follow-up process steps.

elf-aligned Spacer

A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness [X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).] .

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other [Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003). ] .

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

Double Expose, Double Etch (mesas)

This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample. This second layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is therefore a set of photoresist features in between hardmask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration [http://physicsweb.org/press/13777] .

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is [http://imec.be/wwwinter/mediacenter/en/SemiLitho_2007.shtml resist freezing] , which allows a second resist coating over the first developed resist layer. JSR has [http://www.eetimes.com/rss/showArticle.jhtml?articleID=206903526&cid=RSSfeed_eetimes_newsRSS demonstrated] 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.

Certain other double patterning techniques, such as [http://sst.pennnet.com/display_article/323839/5/WNART/none/TETAK/1/Double-development-offers-simpler-double-patterning/ Fujifilm's double development process] , [ K. Derbyshire, Solid State Technology, March 4, 2008.] result in the formation of loops rather than lines and spaces. A second mask would be needed to break these loops into separate lines and spaces.

Double Expose, Double Etch (trenches)

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [http://www.reed-electronics.com/semiconductor/article/CA604512] .

As with the double-expose, double-etch mesas approach, any discrepancy among the different interleaved patterns would be a source of feature-to-feature variation.

Commercial viability

Due to its rather straightforward application, without the need to change the infrastructure, double patterning is not expected to encounter any insurmountable technical or commercialization barriers. Despite the cost and throughput concerns, double patterning has recently received more attention and interest, largely because the maximum numerical aperture (~0.93 in air and ~1.35 in water) for an optical lithography system has been reached.

Double patterning has emerged as a potential way of extending the resolution capability of currently available lithography tools. A state-of-the-art 193 nm tool with a numerical aperture of 1.35 can extend its resolution to 18 nm half-pitch with double patterning. Even electron beam lithography may eventually require double patterning (due to secondary electron scattering) to achieve comparable half-pitch resolution, for instance, in the fabrication of 15 nm half-pitch X-ray zone plates. [ E. Anderson and W. Chao, [http://spie.org/x8367.xml Double exposure makes high-resolution diffractive optics] , SPIE Newsroom, 2007.] Due to this ability to use coarse patterns to define finer patterns, it offers an immediate opportunity to achieve resolution below 30 nm without the need to address the technical challenges of expensive next-generation lithography technologies such as EUV.

Brion Technologies has targeted the double patterning software market down to 22 nm. [ A. Hand, " [http://www.semiconductor.net/article/CA6534848.html Double Patterning Drives Computational Upgrades] ", Semiconductor International, 2/25/2008] Hynix has already endorsed Brion's Tachyon DPT software as a key part of the double patterning solution. [ [http://lw.pennnet.com/Articles/Article_Display.cfm?Section=ONART&PUBLICATION_ID=13&ARTICLE_ID=320972&C=TETAK&dcmp=rss D. Vogler, "Brion powers up to meet DPT challenges at 32nm-22nm Solid State Technology", 2/25/2008] ]

Tela Innovations, a startup founded in 2005 which has recently garnered significant support and funding, specializes in converting arbitrary layouts into array-like features suitable for double patterning. [ M. D. Levenson, " [http://sst.pennnet.com/display_article/321435/5/WNART/none/TETAK/1/SPIE:-Tela-Innovations-lays-it-all-out-straight/ SPIE: Tela Innovations lays it all out straight] ", Microlithograpy World, Feb. 28 2008.]

At the VLSI Technology Symposium in 2007, Samsung reported on a 38 nm half-pitch NAND Flash cell made using dry 193 nm lithography and double patterning on a few critical layers. Using self-aligned double patterning technology, Samsung has produced 30 nm 64 Gb NAND flash devices. [C. Taylor, "Samsung intros 64-Gbit MLC NAND chip," Electronic News, October 23, 2007.]

IM Flash in 2008 began producing 34 nm NAND Flash, [ M. LaPedus, [http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=208400713&pgno=2 Intel, Micron roll 34-nm NAND device] ,EETimes, 5/29/2008.] which is currently only possible in manufacturing fabs with double patterning.

AMD and Texas Instruments have already planned for double patterning as part of their design for manufacturability (DFM) strategies down to the 22 nm node. [ A. Hand, " [http://www.semiconductor.net/article/CA6505600.html DFM, Design Restrictions Enable Double Patterning] " Semiconductor International, 12/1/2007. ]

Intel has been using double patterning in its 45 nm as well as its 65 nm technology. [ D. Vogler, Solid State Technology, [http://sst.pennnet.com/display_article/311942/5/ARTCL/none/TETAK/1/Intel-product-launch-event-yields-more-insight-into-its-manufacturing-strategy/ Intel product launch event yields more insight into its manufacturing strategy] ] [ [http://www.intel.com/technology/itj/2008/v12i2/1-transistors/4-designrules.htm Intel Technology Journal June 17, 2008] ] Double patterning is used to square off the ends of the transistor gates. The first mask pattern consists of the gate lines linked at the ends (an unavoidable consequence of using alternating phase-shift masks). The second mask is a line cutter that separates these into separate gates, using a second photoresist coating. [ [http://www.semiconductor.net/index.asp?layout=talkbackCommentsFull&talk_back_header_id=6493676&articleid=CA6510272 Intel 45 nm process at IEDM] ] The extra steps for the 45 nm double patterning compared to 65 nm are necessary due to the use of dry instead of immersion lithography.

Comparison of patterning options presented by Intel at SPIE 2006: [ Y. Borodovsky, "Marching to the Beat of Moore's Law," SPIE 2006 ]

Triple and Quadruple Patterning

Synopsys has begun consideration of triple patterning decomposition of layers which are less easy to split into two patterns, such as contact layers. [ C. Cork et al., Proc. SPIE, vol. 7028, 702839 (2008).] While only increasing the number of processing steps by 50% (compared to 100% for the insertion of double patterning), triple patterning would enable 16 nm node patterning on a 45 nm node lithography tool. Likewise, quadruple patterning would enable 11 nm node patterning on the same 45 nm node lithography tool, with only 33% additional steps over triple patterning.

References


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