Clock domain crossing


Clock domain crossing

A clock domain crossing (CDC), or simply clock crossing, is when a signal crosses from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.[1]

Synchronizing a signal that crosses into a higher clocked domain can be accomplished by registering the signal through a flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher clocked destination domain. Synchronizing a signal traversing into a slower clock domain is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected.[2]

See also

References

  1. ^ Parker, Roy H., Caution: Clock Crossing A prescription for uncontaminated data across clock domains, Chip Design Magazine, Issue 5, Article 32, July 2004.
  2. ^ Stein, Mike, Crossing the abyss: asynchronous signals in a synchronous world, Paradigm Works, EDN Magazine, 24 July 2003.

External links


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