- Modified Frequency Modulation
- This article is about Modified Frequency Modulation. For other uses of MFM, see the MFM (disambiguation).
Modified Frequency Modulation, commonly MFM, is a line coding scheme used to encode the actual data-bits on most floppy disk formats, hardware examples include Amiga, most CP/M machines as well as IBM PC compatibles. Early hard disk drives also used this coding.
MFM is a modification to the original FM (frequency modulation) scheme for encoding data on single-density floppy disks. Because the minimum spacing between flux transitions is a property of the disk and head design, MFM, which guarantees at most one flux transition per data bit, can be written at higher density than FM, which can require two transitions per data bit. It is used with a data rate of 250 – 500 kbit/s (500 – 1000 kbit/s encoded) on industry standard 5¼" and 3½" ordinary and high density diskettes. MFM was also used in early hard disk designs, before the advent of more efficient types of Run Length Limited (RLL) coding. Except for the steadily disappearing 880 kiB and 1.4 MiB floppy disk formats, MFM encoding is obsolete.
As is standard when discussing hard drive encoding schemes, MFM encoding produces a bit stream which is NRZI encoded when written to disk. A 1 bit represents a magnetic transition, and a 0 bit no transition. There are limits on the minimum and maximum number of 0 bits that may appear between consecutive 1 bits.
MFM encoding can be thought of as having data bits separated by clock bits. The basic encoding rule is that (x, y, z, ...) encodes to (x, x NOR y, y, y NOR z, z, z NOR...). On average this means that each data bit is encoded as two bits on disk, but some delimiters are required at the beginning and end of a sequence, so this limit is never quite reached in practice.
Data ... 0 0 ... ... 0 1 ... ... 1 0 ... ... 1 1 ... Clock bits ...? 1 ?... ...? 0 0... ...0 0 ?... ...0 0 0... MFM encoding ...?010?... ...?0010... ...0100?... ...01010...
Note that the surrounding clock bits are sometimes known, but sometimes require knowledge of the adjacent data bits. A longer example:
Data: 0 0 0 1 1 0 1 1 Clock: ? 1 1 0 0 0 0 0 0 Encoded: ?0101001010001010
(The bold bits are the data bits, the others are the clock bits.)
Notice that there is a minimum of 1 zero bit between adjacent ones (there are never two adjacent one bits), and the maximum number of zeros in a row is 3. Thus, MFM is a (1,3) RLL code.
A special “sync mark” is used to allow the disk controller to figure out where the data starts. This sync mark has two important properties: it has no runs of zeros shorter than 1 or longer than 3 (i.e. it follows the (1,3) RLL rules), and it will never occur in any bit position in any encoded data stream. The sync mark used is called an “A1 sync” since the data bits form the hexadecimal value A1 (10100001).
Data: 1 0 1 0 0 0 0 1 Clock: 0 0 0 1 1 1 0 Encoded: 100010010101001 Sync clock: 0 0 0 1 0 1 0 Sync Mark: 100010010001001 ^ Missing clock bit
The shortest possible sync bit pattern, which follows the (1,3) RLL coding rules but cannot be produced by normal MFM coding, is the first 12 encoded bits of the above: 100010010001.
MMFM, (Modified Modified Frequency Modulation), also abbreviated M²FM, or M2FM, is similar to MFM, but suppresses additional clock bits, producing a longer maximum run length (a (1,4) RLL code). In particular, a clock pulse is only inserted between a pair of adjacent 0 bits if the first bit of the pair did not have a clock pulse inserted before it. In the example below, clock bits that would have been present in MFM are noted in bold:
Data: 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 Clock: 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 Encoded: 01010001001001001000010010001001001000100001
In this system, sync marks are made by inserting additional clock pulses between adjacent zero bits (following the MFM rule) where they would normally be omitted. In particular, the data bit pattern "10001" has a clock pulse inserted in the middle, where it would normally be omitted:
Data: 1 0 0 0 0 1 Normal: 0 1 0 1 0 Sync: 0 1 1 1 0
- ^ Intel Corporation (1977), SBC 202 Double Density Diskette Controller Hardware Reference Manual, pp. 4–26, http://bitsavers.org/pdf/intel/iSBC/9800420A_iSBC_202_Hardware_Reference_Sep77.pdf
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