- X86 architecture
The generic term x86 refers to the most commercially successful
instruction set architecture[Unlike the microarchitecture(and the specific electronic and physical implementation) used for a specific chip design] in the history of personal computing. It derived from the model numbers, ending in "86", of the first few processor generations backward compatible with the original Intel 8086. Since then, many additions and extensions have been added to the x86 instruction set, almost consistently with full backwards compatibility. [Intel abandoned its "x86" naming scheme with the " Pentium" in 1993 (as "numbers" could not be trademarked). However, the term x86 was already firmly established among technicians, compiler writers etc.] The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA, and many others.
As the x86 term became common "after" the introduction of the
80386, it usually implies a binary compatibility with the 32-bit instruction setof the 80386. This may sometimes be emphasized as x86-32to distinguish it either from the original 16-bit x86-16 or from the newer 64-bit x86-64(also called x64). [Intel's naming are IA-32and Intel 64 ( EM64Tor IA-32e) for x86 and x86-64respectively. Likewise, AMD today prefers AMD64over the x86-64name they once introduced.] Although most x86 processors used in "new" personal computers and servers have 64-bit capabilities, to avoid compatibility problems with older computers or systems, the term "x86-64" is often used to denote 64-bit software, with the term "x86" implying only 32-bit. [cite web |title=Linux* Kernel Compiling |url=http://www.intel.com/cd/ids/developer/asmo-na/eng/182333.htm?page=4 |publisher=Intel |accessdate=2007-09-04] [cite web |title=Intel Web page search result for "x64" |url=http://mysearch.intel.com/corporate/default.aspx?culture=en-US&q=x64&searchsubmit.x=21&searchsubmit.y=11 |accessdate=2007-09-04]
Today, the x86 architecture is ubiquitous among desktop and notebook computers, as well as a growing majority among servers and workstations. A large amount of software supports the platform, including OSes such as
MS-DOS, Windows, Linux, BSD, Solaris, and Mac OS X. The architecture is relatively uncommon in embedded systemshowever, and low-cost niches such as appliances and toys lack any significant x86 presence. [The embedded processor's market is populated by more than 25 different architectures, which, due to the price sensitivity, low power and hardware simplicity requirements, outnumber the x86.] Simpler 16-bit x86 chips are more common here, but AMD's Geode CPU and the new Intel Atomare examples of 32-bit designs used in this segment.
Contrary to some popular belief, x86 is not synonymous with IBM PC compatibility as this also implies a multitude of other hardware, albeit with some of it standardized. For instance, the original
Xboxwas designed around an x86 processor but security restrictions led to software requirements making it incapable of simply running standard code designed for other IBM PC compatible systems. Also, the GRID Compasslaptop (one of the first on the market), and many others, used x86 chips before the IBM PC compatible market even started.
The table below lists brands of common [cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |accessdate=2007-08-11] consumer targeted processors implementing the x86
instruction set, grouped by generations that highlight important points in x86 history. Note: "CPU generations are not strict - each generation is roughly marked by significantly improved or commercially successful processor microarchitecturedesigns."
Pointer Registers (S and B)
x86-64-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)
Running X86 Code
x86 code can be test run by placing the code at the
boot sector(ie first sector of the physical disk). x86 binary code can be copied into the boot sector using a sector editor.Boot level running of x86 code provides high privilege first hand access to interrupt calls .As high privilege calls and Interrupt calls running under an operating system environment are hooked versions , the code written on a sterile boot environments may not work under OS.
Offset 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 31 C0 8E D0 66 BC 00 7C FB 66 B8 C0 07 8E D8 90 1ÀŽÐf¼.|ûf¸À.ŽØ 0010 B4 00 B0 00 CD 10 B0 00 B4 05 CD 10 B5 00 B1 07 ´.°.Í.°.´.Í.µ.±. 0020 B4 01 CD 10 B6 09 B2 09 B7 00 B4 02 CD 10 8C D8 ´.Í.¶.².·.´.Í.ŒØ 0030 8E C0 B4 13 B0 00 B7 00 B3 0F B9 0C 00 B6 09 B2 ŽÀ´.°.·.³.¹..¶.² 0040 09 BD 50 00 CD 10 B7 00 B4 08 CD 10 EB FE CD 19 .½P.Í.·.´.Í.ëþÍ. 0050 68 65 6C 6C 6F 20 77 6F 72 6C 64 21 90 90 90 90 hello world!.... 0060 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0070 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0080 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0090 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00A0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00B0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00C0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00D0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00E0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 00F0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0100 41 75 74 68 6F 72 3A 90 90 90 90 90 90 90 90 90 ................ 0110 62 6F 6F 74 40 76 65 6E 74 75 72 6F 6E 2E 6F 72 ................ 0120 67 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0130 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0140 4C 69 6E 6B 73 3A 90 90 90 90 90 90 90 90 90 90 ................ 0150 77 77 77 2E 62 6F 6F 74 6C 65 76 65 6C 2E 62 6C ................ 0160 6F 67 73 70 6F 74 2E 63 6F 6D 90 90 90 90 90 90 ................ 0170 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 0180 77 77 77 2E 76 65 6E 74 75 72 6F 6E 2E 6F 72 67 ................ 0190 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01A0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01B0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01C0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01D0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01E0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 01F0 90 90 90 90 90 90 90 90 90 90 90 90 90 90 55 AA ..............Uª
More Info [ [http://www.bootlevel.blogspot.com Run Hello World] ]
Real mode is an operating mode of
80286and later x86-compatible CPUs. Real mode is characterized by a 20 bit segmented memory address space (meaning that only 1 MB of memory can be addressed), direct software access to BIOSroutines and peripheral hardware, and no concept of memory protectionor multitasking at the hardware level. All x86 CPUs in the 80286series and later start up in real mode at power-on; 80186CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips.
In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for C compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments.
In addition to real mode, the Intel 80286 supports protected mode, expanding addressable
physical memoryto 16 MB and addressable virtual memoryto 1 GB, and providing protected memory, which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index to a segment table. There were two such tables, the Global Descriptor Table(GDT) and the Local Descriptor Table(LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. The segment table provided a 24-bit base address, which can be added to the desired offset to create an absolute address. Each segment can be assigned one of four ring levels used for hardware-based computer security.
Intel 80386introduced support in protected mode for paging, a mechanism making it possible to use virtual memory.
Paging and segmented memory access are required for modern multitasking operating systems.
Linux, 386BSDand Windows NTwere developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series. The success of Windows 3.0, the first widely accepted version of Microsoft Windows, was largely due to its ability to take advantage of 386 features, even though it was used mainly to run multiple sessions rather than to take advantage of the native 32-bit instruction set.
x86 processors that support protected mode boot into
real modefor backward compatibility with the older 8086 class of processors. Upon power-on (aka booting), the processor initiates itself into Real mode, and then it begins loading programs automatically into RAM from ROM and disk. A program inserted somewhere along the boot sequence may be used to put the processor into the Protected mode. The instruction set in protected mode is backward compatible with the one used in real mode.
Virtual 8086 mode
There is also a sub-mode of operation in 32-bit Protected mode, called "
virtual 8086 mode". This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a Protected mode supervisor operating system. This allows for a great deal of flexibility in running both Protected mode programs and real mode programs simultaneously. This mode is available in the 32-bit version of Protected mode; virtual 8086 mode does not exist previously in the 16-bit version of Protected mode, or in the 64-bit long mode.
64-bit Long mode
By 2002, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as video processing and
database engines, while using the 64-bit address, one can directly address 16777216 TB(more than 17 billion GB) of data, although most 64-bit architectures don't support access to the full 64-bit address space (AMD64, for example, supports only 48 bits, split into 4 paging levels, from a 64-bit address). AMD, who would traditionally follow the lead of Intel, took the initiative of extending the 32-bit x86 architecture to 64-bit, initially calling it "x86-64", later renaming it "AMD64". The Opteron, Athlon 64, Turion 64, and later Sempronfamilies of processors use this architecture. The success of the AMD64 line of processors coupled with the lukewarm reception of the IA-64 architecture forced Intel to release their own x86-64 instruction set. Intel had previously developed an x86-64 instruction set [ [http://www.geek.com/intels-yamhill-technology-x86-64-compatible/ Intel's Yamhill Technology: x86-64 compatible | Geek.com ] ] but opted not to enable it in hopes that AMD would not make it to market with theirs before Itanium's new IA-64 instruction set was widely adopted. They branded their extensions "EM64T" architecture, and later re-branded it "Intel 64".
In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as "x64" in the Windows and Solaris operating systems respectively.
Linuxdistributions refer to it either as "x86-64", its variant "x86_64", or "amd64". BSD systems use "amd64" while Mac OS Xuses "x86_64".
Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64 bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.
This was the first time that a "major" upgrade of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.
Floating point unit
Initially, IA-32 included floating-point capabilities only on add-on processors (8087, 80287 and 80387.) With the introduction of the 80486, these 8 80x87 floating point registers, known as ST(0) through ST(7) are built in to the CPU. Each register is 80 bits wide and stores numbers in the double extended precision format of the
IEEE floating-point standard.
These registers are not accessible directly, but are accessible like a
LIFOstack. The register numbers are not fixed, but are relative to the top of the stack; ST(0) is the top of the stack, ST(1) is the next register below the top of the stack, ST(2) is two below the top of the stack, etc. That means that data is always pushed down from the top of the stack, and operations are always done against the top of the stack. Register access had to be done in the stack order, not randomly.
MMX is a
SIMDinstruction set designed by Intel, introduced in 1997 for PentiumMMX microprocessors. It developed out of a similar unit first used on the Intel i860. It first appeared in the Pentium MMX. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video applications.
MMX added 8 new "registers" to the architecture, known as MM0 through MM7 (henceforth referred to as "MMn"). In reality, these new "registers" were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.
Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of "packed data types", which means instead of using the whole register for a single 64-bit integer (
quadword); two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte) may be used. Also because the MMX's 64-bit MMn registers are aliased to the FPU stack, and each of the stack registers are 80-bit wide, the upper 16-bits of the stack registers go unused in MMX, and these bits are set to all ones, which makes it look like NaN's or infinities in the floating point view. This makes it easier to tell whether you are working on a floating point data or MMX data.
In 1997 AMD introduced 3DNow! The introduction of this technology coincided with the rise of 3D entertainment applications and was designed to improve the CPU's
vector processingperformance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's K6 and Athlonseries of processors.
3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses the exact same register naming convention as MMX, that is MM0 through MM7. The only difference is that instead of packing byte to quadword integers into these registers, one would pack
single precisionfloating points into these registers. The advantage of aliasing registers with the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about.
In 1999, Intel introduced the Streaming SIMD Extensions (SSE)
instruction set, following in 2000 with SSE2. The first addition made MMX almost obsolete and the second allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the "Prescott" revision of the Pentium 4processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreadingtechnology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.
SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. ("Note": in AMD64, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.
SSE is a SIMD instruction set that works only on floating point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of
single precisionfloats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack double precisionnumbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128-bit, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.
Physical Address Extension (PAE)
By default, physical addresses are 32-bit, however, there exists a page extension mode called
Physical Address Extensionor PAE, first added in the Intel Pentium Pro, which allows an additional 4 bits of physical addressing. The size of memory in Protected mode is usually limited to 4 GB. Through tricks in the processor's page and segment memory management systems, x86 operating systems may be able to access more than 32-bits of address space, even without the switchover to the 64-bit paradigm. This mode does not change the length of segment offsets or linear addresses; those are still only 32 bits.
x86 virtualization is difficult because the architecture did not meet the Popek and Goldberg requirements until recently. Nevertheless, there are several commercial
x86 virtualizationproducts, such as VMware, Parallels and Microsoft Virtual PC, as well as open sourcevirtualization projects such as QEMU+ KQEMU, VirtualBox, Xen. Other methods, such as the Kernel-based Virtual Machine("KVM"), require newer processors which provide more hardware support for virtualization.
Intel and AMD have introduced x86 processors with hardware-based virtualization extensions that overcome the classical virtualization limitations of the x86 architecture. These extensions are known as Intel VT (IVT or simply VT) that was code named "Vanderpool," and AMD-V that was code named "Pacifica." Although most modern x86 server-based and many modern x86 desktop-based processors include these extensions, the technology is generally considered immature at this point with most software-based virtualization outperforming these extensions. [ [http://www.vmware.com/pdf/asplos235_adams.pdf A Comparison of Software and Hardware Techniques for x86 Virtualization] ] This is expected to change as the technology matures.
x86 assembly language
x86 instruction listings
Real mode— Unreal mode— Virtual 8086 mode— Protected mode— Long mode
List of Intel microprocessors
List of AMD microprocessors
List of VIA microprocessors
List of x86 manufacturers
Input/Output Base Address
* cite conference
first = Keith
last = Adams
coauthors = Agesen, Ole
title = A Comparison of Software and Hardware Techniques for x86 Virtualization
booktitle = Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, 2006
date = 2006-21-2006
url = http://www.vmware.com/pdf/asplos235_adams.pdf
id = ACM 1-59593-451-0/06/0010
accessdate = 2006-12-22
* cite conference
first = Mendel
last = Rosenblum
coauthors = Garfinkel, Tal
title = Virtual machine monitors: current technology and future trends
booktitle = IEEE Computer, volume 38, issue 5
date = May, 2005
url = http://ieeexplore.ieee.org/iel5/2/30853/01430630.pdf?tp=&isnumber=&arnumber=1430630
* [http://www.intel.com/museum/corporatetimeline/index.htm?iid=about+ln_history 25 Years of Intel Architecture]
* [http://www.x86-guide.com/ x86 CPUs guide]
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