Ling adder

In electronics, an adder is a combinatorial or sequential logic element which computes the n-bit sum of two numbers. The family of Ling adders is a particularly fast adder and is designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett Packard presented an innovative 64 bit adder in $0.5\; mu\; m$ CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4. See Naffzinger's paper below for more details.

External links

# H. Ling, " [http://lap.epfl.ch/courses/comparith/Papers/Ling_adder-1966.pdf High Speed Binary Parallel Adder] ", IEEE Transactions on Electronic Computers, EC-15, p.799-809, October, 1966.
# H. Ling, “ [http://www.research.ibm.com/journal/rd/252/ibmrd2502a3I.pdf High-Speed Binary Adder] ”, IBM J. Res. Dev., vol.25, p.156-66, 1981.
# R. W. Doran, " [http://lap.epfl.ch/courses/comparith/Papers/11-doran_carry.pdf Variants on an Improved Carry Look-Ahead Adder] ", IEEE Transactions on Computers, Vol.37, No.9, September 1988.
# N. T. Quach, M. J. Flynn, " [http://lap.epfl.ch/courses/comparith/Papers/Quach-Adder.pdf High-Speed Addition in CMOS] ", IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
# S. Naffziger, “ [http://lap.epfl.ch/courses/comparith/Papers/9-Nafziger-Ling-Adder.pdf A Sub-Nanosecond 0.5um 64b Adder Design] ”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p.362 –363.
# S. Naffziger, " [http://lap.epfl.ch/courses/comparith/Papers/US5719803-Naffziger.pdf High Speed Addition Using Ling's Equations and Dynamic CMOS Logic] ", U.S. Patent No. 5,719,803, Issued: February 17, 1998.