# Buck converter

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Buck converter

A buck converter is a step-down DC to DC converter. Its design is similar to the step-up boost converter, and like the boost converter it is a switched-mode power supply that uses two switches (a transistor and a diode) and an inductor and a capacitor.

The simplest way to reduce a DC voltage is to use a voltage divider circuit, but voltage dividers waste energy, since they operate by bleeding off excess voltage as heat; also, output voltage isn't regulated (varies with input voltage). A buck converter, on the other hand, can be remarkably efficient (easily up to 95% for integrated circuits) and self-regulating, making it useful for tasks such as converting the 12-24V typical battery voltage in a laptop down to the few volts needed by the processor.

Circuit operation

The operation of the buck converter is fairly simple, with an inductor and two switches (usually a transistor and a diode) that control the inductor. It alternates between connecting the inductor to source voltage to store energy in the inductor and discharging the inductor into the load.

Continuous mode

A Buck converter operates in continuous mode if the current through the inductor (IL) never falls to zero during the commutation cycle. In this mode, the operating principle is described by the chronogram in figure 4:

*When the switch pictured above is closed (On-state, top of figure 2), the voltage across the inductor is $V_L = V_i - V_o$. The current through the inductor rises linearly. As the diode is reverse-biased by the voltage source V, no current flows through it;
*When the switch is opened (off state, bottom of figure 2), the diode is forward biased. The voltage across the inductor is $V_L = -V_o$ (neglecting diode drop). The current IL decreases.

The energy stored in inductor L is

$E=frac\left\{1\right\}\left\{2\right\}L imes I_L^2$

Therefore, it can be seen that the energy stored in L increases during On-time (as IL increases) and then decrease during the Off-state. L is used to transfer energy from the input to the output of the converter.

The rate of change of IL can be calculated from:

$V_L=Lfrac\left\{dI_L\right\}\left\{dt\right\}$

With VL equal to $V_i-V_o$ during the On-state and to $-V_o$ during the Off-state. Therefore, the increase in current during the On-state is given by:

$Delta I_\left\{L_\left\{on=int_0^\left\{t_\left\{onfrac\left\{V_L\right\}\left\{L\right\}, dt=frac\left\{left\left(V_i-V_o ight\right)cdot t_\left\{on\left\{L\right\}$

Identically, the decrease in current during the Off-state is given by:$Delta I_\left\{L_\left\{off=int_0^\left\{t_\left\{offfrac\left\{V_L\right\}\left\{L\right\}, dt=-frac\left\{V_ocdot t_\left\{off\left\{L\right\}$

If we assume that the converter operates in steady state, the energy stored in each component at the end of a commutation cycle T is equal to that at the beginning of the cycle. That means that the current IL is the same at t=0 and at t=T (see figure 4).

Therefore, $Delta I_\left\{L_\left\{on+Delta I_\left\{L_\left\{off=0$

So we can write from the above equations:

$frac\left\{left\left(V_i-V_o ight\right)cdot t_\left\{on\left\{L\right\}-frac\left\{V_ocdot t_\left\{off\left\{L\right\}=0$

:It is worth noting that the above integrations can be done graphically: In figure 4, $Delta I_\left\{L_\left\{on$ is proportional to the area of the yellow surface, and $Delta I_\left\{L_\left\{off$ to the area of the orange surface, as these surfaces are defined by the inductor voltage (red) curve. As these surfaces are simple rectangles, their areas can be found easily: $t_\left\{on\right\} imes left\left( V_i-V_o ight\right)$ for the yellow rectangle and $-t_\left\{off\right\} imes V_o$ for the orange one. For steady state operation, these areas must be equal. As can be seen on figure 4, $t_\left\{on\right\}=Dcdot T$ and $t_\left\{off\right\}=T-Dcdot T$. D is a scalar called the "duty cycle" with a value between 0 and 1. This yields:

$left\left(V_i-V_o ight\right)cdot D cdot T -V_o cdot left\left(T-Dcdot T ight\right)=0$

This equation above can be rewritten as:$V_o=Dcdot V_i$

That yields a duty cycle being:

$D=frac\left\{V_o\right\}\left\{V_i\right\}$

From this equation, it can be seen that the output voltage of the converter varies linearly with the duty cycle for a given input voltage. As the duty cycle D is equal to the ratio between tOn and the period T, it cannot be more than 1. Therefore, $V_o leq V_i$. This is why this converter is referred to as "step-down converter".

So, for example, stepping 12v down to 3v (output voltage equal to a fourth of the input voltage) would require a duty cycle of 25%, in our theoretically ideal circuit.

Discontinuous mode

In some cases, the amount of energy required by the load is small enough to be transferred in a time lower than the whole commutation period. In this case, the current through the inductor falls to zero during part of the period. The only difference in the principle described above is that the inductor is completely discharged at the end of the commutation cycle (see figure 5). This has, however, some effect on the previous equations.

We still consider that the converter operates in steady state. Therefore, the energy in the inductor is the same at the beginning and at the end of the cycle (in the case of discontinuous mode, it is zero). This means that the average value of the inductor voltage (VL) is zero, i.e that the area of the yellow and orange rectangles in figure 5 are the same. This yields:

$left\left(V_i-V_o ight\right)Dcdot T-V_ocdot deltacdot T=0$

So the value of δ is:

$delta=frac\left\{V_i-V_o\right\}\left\{V_o\right\}D$

The output current delivered to the load ($I_o$) is constant, as we consider that the output capacitor is large enough to maintain a constant voltage across its terminals during a commutation cycle. This implies that the current flowing through the capacitor has a zero average value. Therefore, we have :

Where is the average value of the inductor current. As can be seen in figure 5, the inductor current waveform has a triangular shape. Therefore, the average value of IL can be sorted out geometrically as follow:

The inductor current is zero at the beginning and rises during tOn up to ILmax. That means that ILmax is equal to:

$I_\left\{L_\left\{Max=frac\left\{V_i-V_o\right\}\left\{L\right\}Dcdot T$

Substituting the value of ILmax in the previous equation leads to:

$I_o=frac\left\{left\left(V_i-V_o ight\right)Dcdot Tleft\left(D+delta ight\right)\right\}\left\{2L\right\}$

And substituting δ by the expression given above yields:

$I_o=frac\left\{left\left(V_i-V_o ight\right)Dcdot Tleft\left(D+frac\left\{V_i-V_o\right\}\left\{V_o\right\}D ight\right)\right\}\left\{2L\right\}$

This latter expression can be written as:

$V_o=V_ifrac\left\{1\right\}\left\{frac\left\{2Lcdot I_o\right\}\left\{D^2cdot V_icdot T\right\}+1\right\}$

It can be seen that the output voltage of a Buck converter operating in discontinuous mode is much more complicated than its counterpart of the continuous mode. Furthermore, the output voltage is now a function not only of the input voltage (Vi) and the duty cycle D, but also of the inductor value (L), the commutation period (T) and the output current (Io).

From discontinuous to continuous mode (and vice versa)

As told at the beginning of this section, the converter operates in discontinuous mode when low current is drawn by the load, and in continuous mode at higher load current levels. The limit between discontinuous and continuous modes is reached when the inductor current falls to zero exactly at the end of the commutation cycle. with the notations of figure 5, this corresponds to :

$Dcdot T + delta cdot T=T$

$D + delta = 1$

Therefore, the output current (equal to the average inductor current) at the limit between discontinuous and continuous modes is (see above):

$I_\left\{o_\left\{lim=frac\left\{I_\left\{L_\left\{maxleft\left(D+delta ight\right)\right\}\left\{2\right\}=frac\left\{I_\left\{L_\left\{max\right\}\left\{2\right\}$

Substituting ILmax by its value:

$I_\left\{o_\left\{lim=frac\left\{V_i-V_o\right\}\left\{2L\right\}Dcdot T$

On the limit between the two modes, the output voltage obeys both the expressions given respectively in the continuous and the discontinuous sections. In particular, the former is

$V_o=Dcdot V_i$

So Iolim can be written as:

$I_\left\{o_\left\{lim=frac\left\{V_ileft\left(1-D ight\right)\right\}\left\{2L\right\}Dcdot T$

Let's now introduce two more notations:
* the normalized voltage, defined by $left|V_o ight|=frac\left\{V_o\right\}\left\{V_i\right\}$. It is zero when $V_o=0$, and 1 when $V_o=V_i$ ;
* the normalized current, defined by $left|I_o ight|=frac\left\{L\right\}\left\{Tcdot V_i\right\}I_o$. The term $frac\left\{Tcdot V_i\right\}\left\{L\right\}$ is equal to the maximum increase of the inductor current during a cycle, i.e the increase of the inductor current with a duty cycle D=1. So, in steady state operation of the converter, this means that $left|I_o ight|$ equals 0 for no output current, and 1 for the maximum current the converter can deliver.

Using these notations, we have:
* in continuous mode, $left|V_o ight|=D$
* in discontinuous mode, $left|V_o ight|=frac\left\{1\right\}\left\{frac\left\{2Lcdot I_o\right\}\left\{D^2cdot V_icdot T\right\}+1\right\}=frac\left\{1\right\}\left\{frac\left\{2left|I_o ight\left\{D^2\right\}+1\right\}=frac\left\{D^2\right\}\left\{2left|I_o ight|+D^2\right\}$;
* the current at the limit between continuous and discontinuous mode is $I_\left\{o_\left\{lim=frac\left\{V_ileft\left(1-D ight\right)\right\}\left\{2L\right\}Dcdot T=frac\left\{I_\left\{o_\left\{lim\right\}\left\{left|I_o ightcdot frac\left\{left\left(1-D ight\right)D\right\}\left\{2\right\}$. Therefore, the locus of the limit between continuous and discontinuous modes is given by $frac\left\{left\left(1-D ight\right)D\right\}\left\{2left|I_o ight=1$.

These expression have been plotted in figure 6. From this, it is obvious that in continuous mode, the output voltage does only depend on the duty cycle, whereas it is far more complex in the discontinuous mode. This is important from a control point of view

Non ideal circuit

The previous study was conducted with the following assumptions:
* The output capacitor has enough capacitance to supply power to the load (a simple resistance) without any noticeable variation in its voltage.
* The voltage drop across the diode when forward biased is zero
* No commutation losses in the switch nor in the diode

These assumptions can be fairly far from reality, and the imperfections of the real components can have a detrimental effect on the operation of the converter.

Output Voltage Ripple

Output voltage ripple is the name given to the phenomenon where the output voltage rises during the On-state and falls during the Off-state. Several factors contribute to this including, but not limited to, switching frequency, output capacitance, inductor, load and any current limiting features of the control circuitry. At the most basic level the output voltage will rise and fall as a result of the output capacitor charging and discharging:

$dV_\left\{o\right\} =frac\left\{icdot dT\right\}\left\{C\right\}$

During the Off-state, the current in this equation is the load current. In the On-state the current is the difference between the switch current (or source current) and the load current. The duration of time (dT) is defined by the duty cycle and by the switching frequency.

For the On-state:

$dT_\left\{on\right\} = D cdot T = frac\left\{D\right\}\left\{f\right\}$

For the Off-state:

$dT_\left\{off\right\} = \left(1-D\right) cdot T = frac\left\{1-D\right\}\left\{f\right\}$

Qualitatively, as the output capacitor or switching frequency increase, the magnitude of the ripple decreases. Output voltage ripple is typically a design specification for the power supply and is selected based on several factors. Capacitor selection is normally determined based on cost, physical size and non-idealities of various capacitor types. Switching frequency selection is typically determined based on efficiency requirements, which tends to decrease at higher operating frequencies, as described below in Effects of non-ideality on the efficiency. Higher switching frequency can also reduce efficiency and possibly raise EMI concerns.

Output voltage ripple is one of the disadvantages of a switching power supply, and can also be a measure of its quality.

Effects of non-ideality on the efficiency

A simplified analysis of the buck converter, as described above, does not account for non-idealities of the circuit components nor does it account for the required control circuitry. Power losses due to the control circuitry is usually insignificant when compared with the losses in the power devices (switches, diodes, inductors, etc.) The non-idealities of the power devices account for the bulk of the power losses in the converter.

Both static and dynamic power losses occur in any switching regulator. Static power losses include $I^2R$ (conduction) losses in the wires or PCB traces, as well as in the switches and inductor, as in any electrical circuit. Dynamic power losses occur as a result of switching, such as the charging and discharging of the switch gate, and are proportional to the switching frequency.

It is useful to begin by calculating the duty cycle for a non-ideal buck converter, which is:

$D = frac\left\{V_o+\left(V_\left\{SWITCH\right\} + V_L\right)\right\}\left\{V_i + V_\left\{SYNCHSW\right\} - V_\left\{SWITCH\right\} - V_L\right\}$

where:

VSWITCH is the voltage drop on the power switch, VSYNCHSW is the voltage drop on the synchronous switch or diode, and VL is the voltage drop on the inductor.

The voltage drops described above are all static power losses which are dependent primarily on DC current, and can therefore be easily calculated. For a transistor in saturation or a diode drop, VSWITCH and VSYNCHSW may already be known, based on the properties of the selected device.

$V_\left\{SWITCH\right\} = I_\left\{SWITCH\right\} cdot R_\left\{ON\right\} = D cdot I_ocdot R_\left\{ON\right\}$
$V_\left\{SYNCHSW\right\} = I_\left\{SYNCHSW\right\} cdot R_\left\{ON\right\} = \left(1-D\right) cdot I_o cdot R_\left\{ON\right\}$
$V_L = I_Lcdot R_\left\{DCR\right\}$

where:

RON is the ON-resistance of each switch (RDSON for a MOSFET), and RDCR is the DC resistance of the inductor.

The careful reader will note that the duty cycle equation is somewhat recursive. A rough analysis can be made by first calculating the values VSWITCH and VSYNCHSW using the ideal duty cycle equation.

Switch resistance, for components such as the Power MOSFET, and forward voltage, for components such as the Insulated Gate Bipolar Transistor (IGBT) can be determined by referring to datasheet specifications.

In addition, power loss occurs as a result of leakage currents. This power loss is simply

$P_\left\{LEAKAGE\right\} = I_\left\{LEAKAGE\right\} cdot V$

where:

ILEAKAGE is the leakage current of the switch, and V is the voltage across the switch.

Dynamic power losses are due to the switching behavior of the selected pass devices (MOSFETs, Power Transistors, IGBTs, etc.). These losses include turn-on and turn-off switching losses and switch transition losses.

Switch turn-on and turn-off losses are easily lumped together as

$P_\left\{SW\right\} = frac \left\{V cdot I_o cdot \left(t_\left\{RISE\right\} + t_\left\{FALL\right\}\right)\right\} \left\{6 cdot T\right\}$

where:

V is the voltage across the switch while the switch is off, tRISE and tFALL are the switch rise and fall times, and T is the switching period.

But this doesn't take in account the parasitic capacitance of the MOSFET which made the "Miller plate." Then, the Switch losses will be more like:

$P_\left\{SW\right\} = frac \left\{V cdot I_o cdot \left(t_\left\{RISE\right\} + t_\left\{FALL\right\}\right)\right\} \left\{2 cdot T\right\}$

When a MOSFET is used for the lower switch, additional losses may occur during the time between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the low-side MOSFET conducts the output current. This time, known as the non-overlap time, prevents "shootthrough", a condition in which both switches are simultaneously turned on. The onset of shootthrough generates severe power loss and heat. Proper selection of non-overlap time must balance the risk of shootthrough with the increased power loss caused by conduction of the body diode.

Power loss on the body diode is also proportional to switching frequency and is

$P_\left\{BODYDIODE\right\} = V_F cdot I_o cdot t_\left\{NO\right\} cdot f_\left\{SW\right\}$

where:

VF is the forward voltage of the body diode, and tNO is the selected non-overlap time.

Finally, power losses occur as a result of the power required to turn the switches on and off. For MOSFET switches, these losses are dominated by the gate charge, essentially the energy required to charge and discharge the capacitance of the MOSFET gate between the threshold voltage and the selected gate voltage. These switch transition losses occur primarily in the gate driver, and can be minimized by selecting MOSFETs with low gate charge, by driving the MOSFET gate to a lower voltage (at the cost of increased MOSFET conduction losses), or by operating at a lower frequency.

$P_\left\{GATEDRIVE\right\} = Q_G cdot V_G cdot f_\left\{SW\right\}$

where:

QG is the gate charge of the selected MOSFET, and VG is the peak gate voltage with respect to ground.

It is essential to remember that, for N-MOSFETs, the high-side switch must be driven to a higher voltage than Vi. Therefore VG will nearly always be different for the high-side and low-side switches.

A complete design for a buck converter includes a tradeoff analysis of the various power losses. Designers balance these losses according to the expected uses of the finished design. A converter expected to have a low switching frequency does not require switches with low gate transition losses; a converter operating at a high duty cycle requires a low-side switch with low conduction losses.

Specific structures

A synchronous buck converter is a modified version of the basic buck converter circuit topology in which the diode, D, is replaced by a second switch, S2. This modification is a tradeoff between increased cost and improved efficiency.

In a standard buck converter, the freewheeling diode turns on, on its own, shortly after the switch turns off, as a result of the rising voltage across the diode. This voltage drop across the diode results in a power loss which is equal to

$P_D = V_D cdot \left(1-D\right) cdot I_o$

where:

VD is the voltage drop across the diode at the load current Io, D is the duty cycle, and Io is the load current.

By replacing diode D with switch S2, which is advantageously selected for low losses, the converter efficiency can be improved. For example, a MOSFET with very low RDSON might be selected for S2, providing power loss on switch 2 which is

$P_\left\{S2\right\} = I_o^2 cdot R_\left\{DSON\right\} cdot \left(1-D\right)$

By comparing these equations the reader will note that in both cases, power loss is strongly dependent on the duty cycle, D. It stands to reason that the power loss on the freewheeling diode or lower switch will be proportional to its on-time. Therefore, systems designed for low duty cycle operation will suffer from higher losses in the freewheeling diode or lower switch, and for such systems it is advantageous to consider a synchronous buck converter design.

Without actual numbers the reader will find the usefulness of this substitution to be unclear. Consider a computer power supply, where the input is 5V, the output is 3.3V, and the load current is 10A. In this case, the duty cycle will be 66% and the diode would be on for 34% of the time. A typical diode with forward voltage of 0.7V would suffer a power loss of 2.38W. A well-selected MOSFET with RDSON of 0.015Ω, however, would waste only 0.51W in conduction loss. This translates to improved efficiency and reduced heat loss.

The advantages of the synchronous buck converter do not come without cost. First, the lower switch typically costs more than the freewheeling diode. Second, the complexity of the converter is vastly increased due to the need for a complementary-output switch driver.

Such a driver must prevent both switches from being turned on at the same time, a fault known as "shootthrough." The simplest technique for avoiding shootthrough is a time delay between the turn-off of S1 to the turn-on of S2, and vice versa. However, setting this time delay long enough to ensure that S1 and S2 are never both on will itself result in excess power loss. An improved technique for preventing this condition is known as adaptive "non-overlap" protection, in which the voltage at the switch node (the point where S1, S2 and L are joined) is sensed to determine its state. When the switch node voltage passes a preset threshold, the time delay is started. The driver can thus adjust to many types of switches without the excessive power loss this flexibility would cause with a fixed non-overlap time.

Multiphase Buck

The multiphase buck converter is circuit topology where the basic buck converter circuit are placed in parallel between the input and load. Each of the "phases" is turned on at equally-spaced intervals over the switching period. This circuit is typically used with the synchronous buck topology, described above.

The primary advantage of this type of converter is that the load current is split among the "n"-phases of the multiphase converter. This load splitting allows the heat losses on each of the switches to be spread across a larger area. Another equally important advantage provided by the multiphase converter is that the output ripple is divided by the number of phases, "n". The load then experiences a ripple frequency which is "n"-times the switching frequency [Guy Séguier, "Électronique de puissance", 7th edition, Dunod, Paris 1999 (in French)] .

This circuit topology is used in computer power supplies to convert the 12VDC power supply to a lower voltage (around 1 V), suitable for the CPU. Modern CPU current requirements exceed 100A and have very tight ripple requirements, less than 10mV. Typical motherboard power supplies use 3 or 4 phases, although control IC manufacturers allow as many as 6 phases [ [http://www.onsemi.com/pub/Collateral/NCP5316-D.PDF NCP5316 4-5-6-phase converter datasheet] ] .

A multiphase topology provides an additional significant benefit. System response to dynamic changes in the load current can be improved significantly, depending on the controller design. Large increases in load current can be addressed by turning on multiple phases, as necessary.

One major challenge inherent in the multiphase converter is ensuring the load current is balanced evenly across the "n"-phases. This current balancing can be performed in a number of ways. Current can be measured "losslessly" by sensing the voltage across the inductor or the lower switch (when it is turned on). This technique is considered lossless because it relies on resistive losses inherent in the buck converter topology. Another technique is to insert a small resistor in the circuit and measure the voltage across it. This approach is more accurate and adjustable, but incurs several costs - space, efficiency and money.

Finally, the current can be measured at the input. Voltage can be measured losslessly, across the upper switch, or using a power resistor, to approximate the current being drawn. This approach is technically more challenging, since switching noise cannot be easily filtered out. However, it is less expensive than emplacing a sense resistor for each phase.

*Boost converter
*Buck-boost converter
*General DC-DC converters

* [http://powerdesigners.com/InfoWeb/design_center/articles/DC-DC/converter.shtm DC-DC Converter Basics] Detailed article on DC-DC converters which gives a more formal and detailed analysis of the Buck including the effects of non-ideal switching (but, note that the diagram of the buck-boost converter fails to account for the inversion of the polarity of the voltage between input and output).
* [http://www.ecircuitcenter.com/Circuits/smps_buck/smps_buck.htm SPICE simulation of the buck converter] .Many Java applets demonstrating the operation of converters are available on the [http://www.ipes.ethz.ch/ipes/e_index.html Interactive Power Electronics Seminar (iPES)]

References

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