- DRTE Computer
The DRTE Computer was a transistorized computer built at the Defence Research Telecommunications Establishment (DRTE), part of the Canadian Defence Research Board. It was one of the earlier fully transistorized machines, running in prototype form in 1957, and fully developed form in 1960. Although the performance was quite good, equal to that of contemporary machines like the PDP-1, no commercial vendors ever took up the design, and the only potential sale to the Canadian Navy's Pacific Naval Laboratories, fell through. The machine eventually ended up on display at the Canada Science and Technology Museum, but the display was later removed and its current fate is unknown.
In the early 1950s transistors had not yet replaced vacuum tubes in most electronics. Tubes varied widely in their actual characteristics, and engineers had developed techniques to ensure that the overall circuit was not overly sensitive to these changes. The same techniques had not yet been developed for transistor-based systems, they were simply too new. While smaller circuits could be "hand tuned" to work, larger systems using many transistors were not well understood. At the same time transistors were still expensive; a tube cost about $0.75 while a similar transistor cost about $8. This limited the amount of experimentation most companies were able to perform.
The DRTE was originally set up to improve communications systems, and to this end they started a research program into using transistors in complex circuits in a new Electronics Lab under the direction of Norman Moody. Between 1950 and 1960s the Electronics Lab became a major center of excellence in the field of transistors, and through an outreach program, the Electronic Component Research and Development Committee, were able to pass on their knowledge to visiting engineers from major Canadian electronics firms who were entering the transistor field.
The key development that led to the eventual construction of the computer was Moody's invention of a new type of flip-flop circuit, a key component of all computer systems. Moody's design used a P-N-P-N junction, consisting of a PNP and NPN transistor connected back-to-back. His design offered much more output power than the common Eccles-Jordan system used up to that time, which was simply a re-implementation of an existing tube-based circuit, replacing the tubes with transistors. The P-N-P-N circuit offered much higher power output, allowing it to drive a number of "downstream" circuits without additional amplifiers. The overall effect was to reduce, sometimes greatly, the total number of transistors needed to implement a digital circuit. One downside, only realized later, is that the current draw of the flip-flop was not balanced, so storing different numbers in them could lead to dramatically different current needs on the power supply—something that should be avoided wherever possible to reduce noise generated when the power draw increases or decreases. At very low power levels, as in a computer, these pulses of noise can be as powerful as the signals themselves. Moody published his circuit in 1956.
Although it appears it was never an official recommendation, by the mid-1950s the DRTE decided that the best way to really develop transistor techniques in a complex system was to build a computer. This was not something they needed for their own use at the time, simply an example of an extremely complex system that would test their capabilities like few other systems could. But as development continued, many of the engineers involved became more interested in computer design than electronics, outside the DRTE's charter and eventually a source of friction between the group and the DRB who funded them.
Starting about 1955, David Florida drove the development of a computer using Moody's flip-flop design. He examined existing computer designs and concluded that the current limitation in computer power was due largely to the burnout rate of the tubes, more tubes meant more frequent burnouts. Although a number of truly massive machines had been built, like SAGE, most machines were much smaller in order to improve uptime. With transistors this limitation was removed; machines could be built considerably more complex with little effect on reliability, as long as one was willing to pay the price for more transistors. With the price falling all the time, Florida's design included every feature he imagined would be useful in a scientific machine.
In particular, the design was to include a number of subsystems for input/output, a binary-coded decimal converter, floating-point hardware including a square root function, a number of loop instructions and index registers to support them, and used a complex three-address instruction format. The three-address system meant that every instruction included the address of up to two operands and the result. Interestingly the system did not include an accumulator, the results of all operations being written back to main memory. This was desirable at the time, when computer memories were generally comparable in speed to the processors (today memory is much slower).
Florida had previously worked with the team building the Manchester Mark 1, and following their lead he designed the DRTE machine with 40-bit words. An instruction was broken down into four 10-bit parts (the instruction and three 10-bit addresses), integers used 39 bits and one for a sign, while floating point numbers had an 8-bit exponent with one bit for the sign and a 32-bit mantissa with one bit for the sign. Florida felt that the three-address instruction format, including the addresses of two parameters and a result, would make programming easier than a register-based system.
An experimental version of the machine consisted of the basic math unit and memory handling. Construction of the complete system started in 1958 and was completed in 1960. The machine ran on a 5 microseconds/cycle lock, or 200 kHz, fairly competitive for a machine of the era. A floating point add took between 50-365 microseconds (μS). The longest instructions, divide or square root, took 5.3 milliseconds (ms) for floating point. Integer adds took about 200 μS, but other operations were handled in subroutines as opposed to hardware and took much longer; a division/square root taking 8.2 ms for instance.
The computer used core memory for all storage, lacking "secondary" systems such as a memory drum. Normally the memory for a machine would be built up by stacking a number of core "planes", each one holding a single bit of the machine's word. For instance, with a 40-bit word as in the DRTE, the system would use 40 planes of core. Addresses would be looked up by translating each 10-bit address into an X and Y address in the planes; for 1,024 words in the DTRE this needed 32×32 planes.
One problem with using core on the DRTE machine was that core required fairly high power in order to operate. Providing such power from transistors, which at the time were low-power only, represented a major challenge. Although one solution, commonly used at the time, was to build the core machinery out of tubes, for the DRTE machine this was considered one more challenge in transistor design. The eventual solution, designed primarily by Richard Cobbald, was entirely transistor-based, and later patented.
Another improvement introduced in their core design involved the handling of the read wire. Reading a location in core works by powering the address in question, in order to write a "1" to that location. If the core was already holding a "1" nothing will happen. However if the core was holding a "0", the power will cause the core to "flip" polarity, and a small extra amount of power will be generated when this happens. A separate line, the read line, will notice this tiny pulse and thus "read" a "0".
One problem with this system is that other cores on the same lines (X or Y) will give off a very small signal as well, potentially masking the signal being looked for. The conventional solution was to wire the read line diagonally back and forth through the plane, so that these smaller signals would cancel out—the positive signal from one would be a negative signal from the next as the wire passed through it in the opposite direction. However this solution also made wiring the core fairly difficult, and considerable amounts of research went into various ways to improve the cost of wiring core.
Cobbald's design made what in retrospect seems like an obvious change; the read wire was threaded across the planes instead of one per plane. In this system the read wire really did pass through only one set of powered lines, and the problems of the "extra signal" were avoided completely. It is not entirely surprising that this solution was not hit on before; cores were constructed a plane at a time and then wired together, whereas this method required the entire core to be built before the read wires could be added. The only major downside to the design is that it required more power to run.
I/O device on the DRTE design were extremely limited, consisting of a Flexowriter for output, and a paper tape reader at about 600 CPS for input. The machine used custom hardware to drive the overall I/O process.
In particular, the system added a hardware binary-to-decimal converter (BDC) that was implemented inline with the I/O systems. This allowed the paper tape to be punched in decimal codes which would be converted invisibly into binary and stored in memory while being read. The reverse was also true, allowing the machine to print the contents of memory directly to tape again. The system was tuned so that the machine could read or write data essentially for free; that is, the system could read and store data as fast as the paper tape could feed it.
The system also offered a crude sort of assembler language support. Using the shift key, characters entered into the system represented mnemonics instead of numerical data, which would then be translated differently. For instance, the letters "AA" would add two floating point numbers, the numbers being stored in the two decimal addresses following. While being read, the paper tape's shift column would signal the BDC to ignore the next codes.
The hardware implementation eventually revealed itself as an anti-feature. If one assumed that all the data being read and written was a decimal representation of binary data the system made perfect sense, but if the data was in some other form, more complex assembler language character codes for instance, it ended up simply added complexity that then had to be turned off. The system was eventually removed when assembler programming became common. It also seriously limited the sorts of devices that could be hooked up, due to the careful tuning of the interface speed.
Further development and use
Parallel math unit
As soon as the prototype math unit was completed in 1957, a new unit that operated on an entire word in parallel was started. This new unit was ready around the same time as the "full version" of the machine (1960–61) and was later retrofitted into the design. This improved speeds by about ten times, for instance a floating point add not took 40 microseconds (from 300), multiplication 180 (from 2.2 ms) and a square root 510 microseconds (from 5.3 ms). Integer math was likeways improved by about the same factor, although "complex" arithmetic like multiplication remained in code as opposed to hardware. With the new math unit the machine was faster than the average contemporary system, although slower than "high end" machines like the IBM 7090 by about two to five times.
As with any research machine, the DRTE system was used for a number of "household" calculations, as well as the development of a number of simple computer games. These included tic-tac-toe and hangman, as well as a simple music generator that could play the Colonel Bogey March by attaching a speaker to a particular flip-flop.
In the late 1950s the US was in the midst of rolling out the SAGE system, and became interested in the effects of aurora borealis on radar operation. An agreement was eventually signed between the DRB and US Air Force, with the Air Force providing two million dollars to build a radar research center modelled on MIT's Lincoln Laboratory, which had provided much of the US technical lead in radar systems. The DRB proposed a site between five and six hundred miles from Fort Churchill, which was already being used for extensive aurora research with their rocketry program, allowing the radars to directly measure the effects of aurora on radar by tracking the rocket launches. Eventually a site outside Prince Albert, Saskatchewan was selected, perhaps due to it being the current Prime Minister's, John Diefenbaker, home riding. The new site was opened in June 1959, known as the Prince Albert Radar Laboratory, or PARL.
In order to quickly record data during test runs, the DRTE built a custom system known as DAR, the Digital Analyzer and Recorder. DAR was a fairly high-priority project, and some of the manpower originally working on the DRTE computer were put on DAR instead. The machine itself consisted of a non-programmable computer that read the data into 40,000 bits of core memory, tagged it with timecode and other information, and then wrote it to magnetic tape. DAR was used for a number of years, and had to be rebuilt after a fire in 1962.
In 1958 the DRB sent a proposal to NASA to launch a "topside sounder", which would take measurements of the Earth's ionosphere from space. This was a topic of some importance at the time; the DRB was conducting a major ionospheric research program in order to build a very-long distance communications system (which would later be used on the Mid-Canada Line and DEW Line). The various US agencies that commented on the system were highly sceptical that the DRB could build such a device, but suggested they do so anyway as a backup to their own much simpler design. In the end the US design ran into lengthy delays, and the "too advanced" Canadian design was eventually launched in 1962 as Alouette I.
While Alouette was being designed, a major question about the lifetime of the solar cells powering the system came to be solved on the DRTE computer. They developed a program that simulated the effects of precession on the satellite's orbit, and used this information to calculate the percentage of time that sunlight fell on it. The result proved the system would have more than enough power, and in fact while it was designed with a lifetime of only one year, Alouette I eventually ran for ten before being shut off.
The computer was also put into use generating tracking commands for the receiver dish antenna in Ottawa that downloaded data from Alouette. The antenna could not track through "straight up", and had to be rotated 180 degrees to track back down to the opposite horizon. The movement was controlled by a simple system reading a paper tape, so the computer was used to produce the tapes so the dish would be slowly rotated as it tracked the satellite, thereby guaranteeing no "dead time". Eventually a library of tapes was built up for any possible pass.
- The DRTE Computer - excellent in-depth article on the machine and its history, this article is based on an unpublished report for the Canada Science and Technology Museum, written by John Vardalas in 1985
- Dirty Gertie: The DRTE Computer - smaller article by Linda Petiot
- The Prince Albert Radar Laboratory
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Prince Albert Radar Laboratory — The Prince Albert Radar Laboratory (PARL) was a radar research facility operated by the Defence Research Telecommunications Establishment (DRTE), part of the Canadian Defence Research Board. Its primary purpose was to test long range radio… … Wikipedia