AMD K10

The AMD K10 is AMD's latest microprocessor architecture. Though there were once reports that the K10 had been cancelled [http://www.theinquirer.net/?article=27421 AMD's K10 is delayed or dead] , The Inquirer] , the first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November 11, 2007 as the immediate successors to the AMD K8 series of processors (Athlon 64, Opteron, 64-bit Sempron).

Nomenclatures

It is commonly perceived that from the time after the use of the codename "K8" for the AMD K8 or Athlon 64 processor family, AMD no longer uses K-nomenclatures (originally stood for Kryptonite Fact|date=May 2008) since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005.

The name "K8L" was first coined by Charlie Demerjian, one of the writers of "The Inquirer" back in 2005 [ [http://www.theinquirer.net/default.aspx?article=27421 The Inquirer report] ] , and was used by the wider IT community as a convenient shorthand cite news |last=Valich |first=Theo |title=AMD explains K8L misnomer |url=http://www.theinquirer.net/default.aspx?article=37444 |publisher=The Inquirer |accessdate=2007-03-16] along with "Stars", as the codenames for desktop line of processors was named under stars or constellations, while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology" [ [http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~111541,00.html Official Announcement of "AMD Next Generation Processor Technology"] ] .

In a video interview [ [http://www.syndrome-oc.net/articles.php?article=94&lang=en Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA)] in February 2007] ] , Giuseppe Amato confirmed that the codename is K10.

It was revealed, by The Inquirer itself, that the codename "K8L" referred to a low-power version of the K8 family, later named Turion 64, and that K10 was the official codename for the microarchitecture .

AMD refers to it as Family 10h Processors, as it is the successor of the Family 0Fh Processors (codename K8). 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0Fh (h represents hexadecimal numbering) equals the decimal number 15, and 10h equals decimal 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family identifier number.)

chedule of launch and delivery

Timeline

Historical information

In 2003, AMD outlined the features for upcoming generations of microprocessors after K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003 [ [http://pc.watch.impress.co.jp/docs/2006/0119/kaigai233_01l.gifMicroprocessor Forum 2003 presentation slide] ] . The outlined features to be deployed by the next-generation microprocessors are as follows:

* Threaded architectures
* Chip level multiprocessing
* Huge scale MP (multi-processor) machines
* 10 GHz operation
* Much higher performance superscalar, out of order CPU core
* Huge caches
* Media/vector processing extensions
* Branch and memory hints
* Security and virtualization
* Enhanced Branch Predictors
* Static and dynamic power management

On April 13, 2006, Henri Richard, AMD executive vice president and chief officer for marketing and sales, acknowledged [cite web |last=Hall |first=Chris |title=Re-defining microprocessors: Q&A with AMD’s Henri Richard |url=http://www.digitimes.com/bits_chips/a20060313PR201.html |publisher=DigiTimes.com |accessdate=2007-03-18] the existence of the new microarchitecture in an interview.

In June 2006, AMD executive vice president Henri Richard had another interview with "DigiTimes" commented on the upcoming processor developments:

Cquote2|Q: What is your broad perspective on the development of AMD processor technology over the next three to four years?

A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on.|AMD Executive Vice President, Henri Richard|Source: DigiTimes Interview with Henri Richard [ [http://www.digitimes.com/news/a20060628VL201.html AMD's vision for next few years] - an interview with Henri Richard]

Confirmation of time frames

On July 21 2006, AMD President and Chief operating officer (COO) Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of new microprocessors of "Revision H" under the new microarchitecture is slated for the middle of 2007; and that it will contain a quad core version for servers, workstations, and high-end desktops, as well as a dual core version for consumer Desktops. Some of the "Revision H" Opterons shipped in 2007 will have a thermal design power of 68 W.

On August 15 2006, at the launch of the first Socket F dual-core Opterons, AMD announced that the firm had reached the final design stage (tape-out) of quad-core Opteron parts. The next stages are testing and validation, with sampling to follow after several months. [cite news | url=http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=191902502 | title=Next-Generation AMD Opteron Paves The Way For Quad-Core | publisher=crn.com | date=2006-08-15]

On June 29 2007, AMD stated that server processors codenamed "Barcelona" will ship in August 2007, and corresponding server systems from partners will ship in September of the same year. [cite news | url=http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~118193,00.html | title=AMD to Ship Industry’s First Native x86 Quad-Core Processors In August | publisher=amd.com | date=2007-06-29]

On August 13, the reported ship dates for the first Barcelona processors were set for September 10, 2007. They announced the Opteron 2348 and 2350 will have core frequencies of 1.9 GHz and 2.0 GHz. [cite news | url=http://www.tgdaily.com/content/view/33338/139/ | title=AMD to launch two Barcelona-based processors in September | publisher=tgdaily.com | date=2007-08-13]

Internal codenames

As of November 2006, reports leaked the upcoming desktop part codenames "Agena", "Agena FX", and the core speeds of the parts range from 2.4 GHz - 2.9 GHz respectively, 512 KiB L2 cache each core, 2 MiB L3 cache, using HyperTransport 3.0, with a TDP of 125 W. [cite news | url=http://www.hkepc.com/bbs/itnews.php?tid=678736 | title=AMD Quad-Core Altair upcoming in 2007 Q3 | publisher=HKEPC | date=2006-10-03] In recent reports, single core variants (codenamed "Spica") and dual core with or without L3 cache (codenamed "Kuma" and "Rana" respectively) are available under the same microarchitecture [cite news | url=http://www.hkepc.com/bbs/itnews.php?tid=679375 | title=AMD to enter K10 era in 2H 2007 | publisher=HKEPC | date=2006-10-04] .

During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server, desktop and mobile processors.cite news | url=http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Dec 06A-DayMartySeyer.pdf | title=2006 Analyst Day Slides (Roadmaps for server and mobile | publisher=AMD |format=PDF] For the servers segment, AMD will unveil two new processors based on the architecture codenamed "Barcelona" and "Budapest" for more than 1-way and 1-way servers respectively . For the second half of 2007, HyperTransport 3.0 and Socket AM2+ will be unveiled, which are designed for the specific implementation of the aforementioned consumer quad core desktop chip series, with naming convention changes from city names (up to middle of 2007) to stars or constellations after that, such as "Agena"; in addition, the AMD Quad FX platform and its immediate successor will support the high end enthusiast dual-processor versions of the chip, codenamed as "Agena FX", updates the processors line for AMD Quad FX platform. As with the server chips codenamed "Barcelona", the new desktop quad core series will feature a shared L3 cache, 128-bit floating point (FP) units and an enhanced microarchitecture. "Agena" will be the native quad-core processor for the desktop. "Kuma", a dual-core variant will follow on in Q3 while "Rana", the dual-core version with no shared L3 cache is expected at the end of the year.

ubsequent product launches

More information about the upcoming chip codenamed "Montreal" on the server roadmap [ [http://theinquirer.net/default.aspx?article=38634 The Inquirer report] ] using MCM technique of two "Shanghai" cores with a total of 12 MiB L3-cache [ [http://www.fudzilla.com/index.php?option=com_content&task=view&id=529&Itemid=1 FudZilla report] ] codenamed AMD K10.5 [ [http://www.fudzilla.com/index.php?option=com_content&task=view&id=496&Itemid=35 FudZilla report] ] . The desktop variant for "Shanghai" is codenamed "Ridgeback" [ [http://www.fudzilla.com/index.php?option=com_content&task=view&id=2214&Itemid=1 Fudzilla report] , retrieved August 1, 2007] . Afterwards is the release of products based on the "Bulldozer" cores, which is optimized with integrated graphics core (AMD Fusion) or native octal-core (8 core) server architecture (codenamed "Sandtiger"), and the "Bobcat" core, optimized for low-power operations.

Change of model nomenclatures

During Computex 2007 in early June, new information regarding the naming schemes of upcoming AMD microprocessors emerged. Additional letters indicating both performance and power envelope will precede the 4 digit model number [cite news | url=http://blog.wired.com/gadgets/2007/06/how_to_decipher.html | title=How to decipher AMD's new CPU naming code | publisher=Gadget Lab | date=2007-06-04] .

The model numbers of the new line of processors were apprently changed from the PR ratings used by its predecessors, the Athlon 64 series processors (except Phenom FX series, being suggested to follow the nomenclature of Athlon 64 FX series). As reported by DailyTech [http://dailytech.com/AMD+Expands+Upcoming+Processor+Branding/article7537.htm DailyTech report] ] , the model numbers are in alpha-numeric format as AA-@### where AA are alphabetical letters, the first letter indicating the processor class and the second indicating the typical TDP power envelope. The character @ is the series indicator, which varies by branding (see below table), and the last three characters (###) are the model number, with higher numbers indicating greater performance.

Not much information was known about the details of the model numbers, but the processors will be divided into three segments: Premium, Intermediate, and Value. Premium segment model numbers have processor class "G", Intermediate segment "B", and Value level "L", as discovered on the web from the AsRock website [ [http://xtreview.com/images/athlon-X2-BE-235001-3.gifXTReview
] ] . Similarly, three levels of TDP, "more than 65W", "65W", and "less than 65W", are indicated by the letters "P", "S", and "E" respectively [http://dailytech.com/AMD+Expands+Upcoming+Processor+Branding/article7537.htm DailyTech report] ] .

As of November 2007, AMD has removed the letters from the model names and X2/X3/X4 monikers for depicting the number of cores of the processor, leaving just a four digit model number with the first character being the sole identification of the processor family cite web | url=http://www.vr-zone.com/articles/AMD_Revised_Desktop_Model_Number_Structure/5330.html | title=AMD Revised Desktop Model Number Structure | publisher=VR-Zone | date=2007-10-09] , while Sempron remained using the LE prefix, as follows:

Live demonstrations

On November 30, 2006, AMD live demoed the native quad core chip known as "Barcelona" for the first time in public, [cite news | url=http://news.com.com/2061-10791_3-6139758.html | title=AMD Demonstrates Its Quad Core Server Chips | publisher=CNET.com | date=2006-11-30] while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than Intel Xeon 5355 processor codenamed "Clovertown" [cite news | url=http://www.legitreviews.com/article/426/1/ | title=AMD Demonstrates Barcelona; The First True, Native Quad Core Opteron | publisher=legitreviews.com | date=2006-11-30] . More details regarding this first revision of the next generation AMD microprocessor architecture have surfaced on the web recently including their clock speeds. [cite news | url=http://arstechnica.com/news.ars/post/20061206-8363.html | title=Quick Look at AMD Quad Core Barcelona | publisher=arstechnica.com | dat=6 December 2006] [ [http://theinquirer.net/default.aspx?article=36195 The Inquirer article] ]

On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed "Clovertown" dual-processor (2P) quad-core processors [cite news | url=http://www.dailytech.com/article.aspx?newsid=5863 | title=AMD Expects Quad Core Barcelona to Outperform Clovertown by 40% | publisher=dailytech.com | date=2007-01-25] . The expected performance of floating point per core would be approximately 1.8 times that of the K8 family, at the same clock speed [cite news | title=Go to 'Barcelona' over 'Cloverton' | url=http://news.com.com/AMD+Go+to+Barcelona+over+Clovertown+-+page+2/2100-1006_3-6152645-2.html?tag=st.num | publisher=CNET.com | date=2007-01-23] .

On May 10 2007, AMD held a private event demonstrating the upcoming processors codenamed "Agena FX" and chipsets, with one demonstrated system being AMD Quad FX platform with one Radeon HD 2900 XT graphics card on the upcoming RD790 chipset, the system was also demonstrated real-time converting a 720p video clip into another undisclosed format while all 8 cores were maxed at 100% by other tasks. [ [http://www.tgdaily.com/index.php?option=com_content&task=view&id=31977 TGDaily report] ]

ister microarchitecture

Also due in a similar time frame will be a sister microarchitecture, which will focus on lower power consumption chips in mobile platforms as well as small form factor features. This microarchitecture will contain specialized features such as mobile optimized crossbar switch and memory controller and other on-die components; link power management for HyperTransport 3.0; and others. At that time, AMD simply dubbed it "New Mobile Core", without giving a specific codename.

On the December 2006 analyst day, Executive vice president Marty Seyer announced the new mobile core codenamed "Griffin" to be launched in 2008 with inherited power optimizations technologies from the K10 architecture, but based on a K8 design [cite news | url=http://www.informationweek.com/management/showArticle.jhtml?articleID=196604355 | title=AMD updates Opteron, Turion roadmaps | publisher=informationweek.com | date=2006-12-14] .

Iterations of the release

In late 2007 to second quarter of 2008, there will be a modification to the core to be fabricated at 45 nm process node [cite news | url=http://www.pcpro.co.uk/news/93934/amd-outlines-its-quadcore-computing.html | title=AMD Outlines Quad Core Computing | publisher=www.pcpro.co.uk | date=2006-09-19] , with enhancements such as FB-DIMM support, Direct Connect Architecture 2.0, enhanced Reliability, Availability and Serviceability (RAS), and probably more for the processor die. The platform will also add support for I/O Virtualization, PCI Express 2.0, 10 Gigabit NIC, larger caches, and more.

However, reports have suggested that FB-DIMM support had been dropped from future roadmaps of the majority of AMD products since popularity is low [cite news | url=http://www.theinquirer.net/default.aspx?article=34220 | title=Intel Pulls Back from FB-DIMM | publisher=inquirer.net | date=2006-09-07] [cite news | url=http://www.legitreviews.com/news/2665/ | title=No Shocker Here | publisher=legitreviews.com | date=2006-09-15] . Also, FB-DIMM's future as an industry standard had been called into question.

An article published by The Inquirer corroborates the earlier reports of the timeline (as cited in this article). According to the report, there will be three iterations of the server processor core: one named "Barcelona", due in Q2 of 2007, with new CPU core components as well as the microarchitecture, but built on the old HyperTransport 2.0 infrastructure; the second is "Budapest" for single socket systems using socket AM2+ or socket AM3, with HyperTransport 3.0; and the third, codenamed "Shanghai" is an update of the server chip, based on 45 nm process [ [http://www.dailytech.com/article.aspx?newsid=5984 DailyTech report] ] , probably also with HyperTransport 3.0 and DDR3 implementation, due in Q1-Q2 2008. [cite news | url=http://www.theinquirer.net/default.aspx?article=34433 | title=AMD Quad Cores: The Whole Story Unfolded | publisher=inquirer.net | date=2006-09-16]

AMD, on September 17, 2007, announced [ [http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~120741,00.html AMD announcement] , retrieved September 17, 2007] that a three core (triple-core) processor will also be released under the Phenom brand lineup, codenamed "Toliman". AMD official replied in an interview that this product is benefitted from ATI technologies to add fuses to the quad-core processor and shutting down one of the four cores [ [http://www.computerworld.com.au/index.php/id;1316491511;pp;6;fp;2;fpid;4 ComputerWorld report] , retrieved October 9, 2007] to become a triple-core processor, which the technique has been popular for making one or more mainstream GPU cores from a single high-end GPU core by blowing out parts of the circuit to save R&D costs while targeting more markets some time ago. The triple-core processor still see the same specifications for quad-core variants, the naming of the processor lineup, according to the AMD branding scheme, will be named as Phenom triple-core 8000 series, the processor line will be focused on what AMD called the fourth market segment or the "High-end Mainstream" segment beside Value, Mainstream and Performance segments in an interview with BetaNews, which the targeted customers of the processors are "those who are willing to pay more for more performance but not required for too much processing power as required by gamers and system builders [ [http://www.betanews.com/article/AMD_Makes_Wildcard_Play_with_TripleCore_Phenom/1190069821 BetaNews report] , retrieved September 17, 2007] [ [http://www.betanews.com/article/Interview_AMDs_Simon_Solotko_and_the_Third_Core/1190073550 BetaNews interview] , retrieved September 17, 2007] , while there are single core (Sempron) variants for low-end market, and dual-core (Athlon) variants for mid-range market, and quad-core (Phenom quad-core 9000 series and Phenom FX) variants should be seen in the high-end market at the same time frame.

Further in 2008, AMD will introduce "Deneb FX" for the replacement for the AMD Quad FX platform, as well as "Deneb" for the mainstream. "Propos" and "Regor" will also replace "Kuma" and "Rana" in the lower market segments. Socket AM2+ being named in the late 2006 might actually have been the original AM3 socket, but as naming conventions changed, so that the next generation of consumer desktop socket capable of DDR3 will be socket AM3. [cite news | url=http://www.dailytech.com/AMD+45nm+DDR3+and+Socket+AM3+in+2008/article7132c.htm | title=AMD: 45nm, DDR3, and AM3 in 2008 | publisher=dailytech.com | date=2007-05-02]

Features

Fabrication technology

AMD will introduce the microprocessors manufactured at 65 nm feature width using Silicon-on-insulator (SOI) technology, since the release of K10 coincides with the volume ramp of this manufacturing process [cite news | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734 | title=An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm process and AM2 Performance | publisher=AnandTech |date=2006-04-04] . The servers will be produced for Socket F(1207) or later 1207-pin socket infrastructure, the only server socket on AMD's near-term roadmap; the desktop parts will come on Socket AM2 or Socket AM2+.

AMD announced during the Technology Analyst Day [ [http://www.amd.com/us-en/Corporate/InvestorRelations/0,,51_306_14047,00.html 2006 AMD Analyst Day 2006 page] ] that the use of Continuous Transistor Improvement (CTI) and Shared Transistor Technology (STT) would finally lead to the implementation of Silicon-Germanium-On-Insulator (SGoI) on 65 nm process CPUs [cite web |last=Ostrander |first=Daryl |title=2006 Technology Analyst Day Slides |url=http://www.amd.com/us-en/assets/content_type/DownloadableAssets/DarylOstranderAMDAnalystDay.pdf |publisher=Advanced Micro Devices |accessdate=2007-03-19|format=PDF] .

upported DRAM standards

The K8 family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die memory controller (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. DDR2 RAM introduces some additional latency over traditional DDR RAM since the DRAM is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on CAS latency alone are not sufficient. For example, Socket AM2 processors are known to demonstrate similar performance using DDR2 SDRAM as Socket 939 processors that utilize DDR-400 SDRAM. K10 processors support DDR2 SDRAM rated up to DDR2-1066 (1066 MHz) [cite news |title=AMD’s next-generation Star supports DDR2-1066 & SSE4a |url=http://www.hkepc.com/bbs/itnews.php?tid=718770 |publisher=HKEPC Hardware |accessdate=2007-03-19] .

Higher computational throughput

It was also reported by several sources (such as AnandTech, The Inquirer and Geek.com) that the microprocessors implementing the microarchitecture will feature a doubling in the width of SSE execution units in the cores. With the help of major improvements in the memory subsystem (such as load re-ordering and improved prefetch mechanisms) as well as the doubled instruction fetch and load, it is expected to increase the suitability of the processor to scientific and high-performance computing tasks and potentially improve its competitiveness with Intel's Xeon, Core 2, Itanium 2 and other contemporary microprocessors.

Many of the improvements in computational throughput of each core are listed below.

Characteristics of the microarchitecture

[cite news |last=Shimpi |middle=Lal |first=Anand |url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2939 |title=Barcelona Architecture: AMD on the Counterattack |publisher=AnandTech |accessdate=2007-03-18]
*Form factors
** Socket AM2+ for Athlon dual-core 6000 series, Phenom quad-core processors as well as single-socket Opterons and Socket 1207 FX for Phenom FX processors targeted at the AMD Quad FX platform as well as multi-socket Opterons, supporting HyperTransport 3.0 with the use of DDR2 DIMMs [cite news | url=http://www.hkepc.com/bbs/itnews.php?tid=678736 | title=AMD Quad-Core Altair upcoming in 2007 Q3 | publisher=HKEPC | date=2006-10-03] .
** Backward-compatible with existing Socket AM2 and Socket F motherboards.

*Instruction set additions and extensions
** New bit-manipulation instructions: Leading Zero Count (LZCNT) and Population Count (POPCNT)
** New SSE instructions named as "SSE4a": combined mask-shift instructions (EXTRQ/INSERTQ) and scalar streaming store instructions (MOVNTSD/MOVNTSS). These instructions are not found in Intel's SSE4
** Support for unaligned SSE load-operation instructions (which formerly required 16-byte alignment) [cite news |last=Case |first=Loyd |title=AMD Unveils Barcelona Quad-Core Details |url=http://www.channelinsider.com/article/AMD+Unveils+Barcelona+QuadCore+Details/191008_2.aspx |publisher=Ziff Davis |accessdate=2007-03-18]

*Execution pipeline enhancements
** 128-bit wide SSE units
** Wider L1 data cache interface allowing for two 128-bit loads per cycle (as opposed to two 64-bit loads per cycle with K8)
** Lower integer divide latency
** 512-entry indirect branch predictor and a larger return stack (size doubled from K8) and branch target buffer
** Side-Band Stack Optimizer, dedicated to perform increment/decrement of register stack pointer
** Fastpathed CALL and RET-Imm instructions (formerly microcoded) as well as MOVs from SIMD registers to general purpose registers

*Integration of new technologies onto CPU die:
** Four processor cores (Quad-core)
** Split power planes for CPU core and memory controller/northbridge for more effective power management, first dubbed "Dynamic Independent Core Engagement" or "D. I. C. E." by AMD and now known as "Enhanced PowerNow!", allowing the cores and northbridge (integrated memory controller) to scale power consumption up or down independently [ cite news | url=http://www.hardocp.com/article.html?art=MTE0OCwsLGhlbnRodXNpYXN0 | title=AMD Next Generation Processor Technology Slides | publisher=HardOCP | date=2006-08-22] .
** Shutting down portions of the circuits in core when not in load, named "CoolCore" Technology.

*Improvements in the memory subsystem:
**Improvements in access latency:
*** Support for re-ordering loads ahead of other loads and stores
*** More aggressive instruction prefetching, 32 bytes instruction prefetch as opposed to 16 bytes in K8
*** DRAM prefetcher for buffering reads
*** Buffered burst writeback to RAM in order to reduce contention
**Changes in memory hierarchy:
*** Prefetch directly into L1 cache as opposed to L2 cache with K8 family
*** 32-way set associative L3 victim cache sized at least 2 MiB, shared between processing cores on a single die (each with 512 KiB of independent exclusive L2 cache), with a sharing-aware replacement policy.
*** Extensible L3 cache design, with 6 MiB planned for 45 nm process node, with the chips codenamed "Shanghai".
**Changes in address space management:
*** Two 64-bit independent memory controllers, each with its own physical address space; this provides an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environments. This approach is in contrast to the previous "interleaved" design, where the two 64-bit data channels were bounded to a single common address space.
*** Larger Tagged Lookaside Buffers; support for 1 GiB page entries and a new 128-entry 2 MiB page TLB
*** 48-bit memory addressing to allow for 256 TiB memory subsystems
*** Memory mirroring, data poisoning support and Enhanced RAS
*** Nested page tables for AMD-V virtualization technology, claimed to have decreasing world switch time by 25%.

*Improvements in system interconnect:
** HyperTransport retry support
** Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.

*Platform-level enhancements with additional functionality:
** Five p-states allowing for automatic clock rate modulation
** Increased clock gating
** Official support for coprocessors via HTX slots and vacant CPU sockets through HyperTransport: Torrenza initiative.

uccessor

Codenamed "Fusion" is a CPU technology furthering the trend of continued system component integration onto CPU die (which was initiated by K8 with integrated System Request Queue (SRQ), cross-bar switch, memory controller as well as HyperTransport links), planned beyond these two aforementioned families of products, and will be due in late 2008 or sometime in 2009. The Fusion products will see new processor cores, codenamed "Bulldozer" and "Bobcat" incorporated into the die.

Media discussions

"Note": These media discussions are listed in ascending date of publication.

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ee also

* Phenom (processor)
* List of AMD Phenom microprocessors
* List of AMD Athlon X2 microprocessors

References

External links

* [http://www.amd.com/ AMD Official Website]
* [http://multicore.amd.com/us-en/quadcore/ AMD Quad-core processors introduction]
* [http://www.dvhardware.net/article2023.html DarkVision Hardware: AMD talks about K9, K10 future innovations]
* [http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~111541,00.html Next-Generation AMD Opteron Processors Introduced with Record OEM Design Wins and Native Quad-Core Upgrade Path (Official AMD press release on 15 August 2006)]
* [http://pc.watch.impress.co.jp/docs/2006/0202/kaigai238.htm PC Watch report about K10 based on AMD Technology Analyst Day 2004 and 2005] jp icon
* [http://pc.watch.impress.co.jp/docs/2006/0119/kaigai233.htm PC Watch report about K10 based on Slides presented in Microprocessor Forum 2003] jp icon
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* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40546.pdf Software Optimization Guide for AMD Family 10h Processors]
* [http://techreport.com/etc/2005q4/amd-direction/index.x?pg=1 TechReport: AMD outlines Future Goals]
* [http://www.tweaktown.com/forums/archive/index.php/t-9833.html TweakTown Discussions (2003)]
* [http://www.xbitlabs.com/articles/cpu/display/amd-k10.html X-bit labs: AMD K10 Micro-Architecture]