Magnetic-core memory


Magnetic-core memory
A 32 x 32 core memory plane storing 1024 bits of data.
Computer memory types
Volatile
Non-volatile

Magnetic-core memory was the predominant form of random-access computer memory for 20 years (circa 1955-75). It uses tiny magnetic toroids (rings), the cores, through which wires are threaded to write and read information. Each core represents one bit of information. The cores can be magnetized in two different ways (clockwise or counterclockwise) and the bit stored in a core is zero or one depending on that core's magnetization direction. The wires are arranged to allow an individual core to be set to either a "one" or a "zero", and for its magnetization to be changed, by sending appropriate current pulses through selected wires. The process of reading the core causes the core to be reset to a "zero", thus erasing it. This is called destructive readout.

Such memory is often just called core memory, or, informally, core. Although core memory had been superseded by semiconductor memory by the end of the 1970s, memory is still occasionally called "core"; in particular, a file recording the contents of memory after a system error is usually called a core dump.

Contents

History

Frederick Viehe applied for various patents on the use of transformers for building digital logic circuits in place of relay logic beginning in 1947, issued through 1960, and assigned to IBM, working in his home laboratory. The first application was the Electronic Relay Circuit, revised and called the Memory Transformer. He was issued a patent for core memory manufacture in 1966.[1] Independently, substantial work in the field was carried out by the Shanghai-born American physicists An Wang and Way-Dong Woo, who created the pulse transfer controlling device in 1949.[2] The name referred to the way that the magnetic field of the cores could be used to control the switching of current in electro-mechanical systems. Wang and Woo were working at Harvard University's Computation Laboratory at the time but, unlike MIT, Harvard was not interested in promoting inventions created in their labs. Instead Wang was able to patent the system on his own.

The MIT Whirlwind computer required a fast memory system for real-time aircraft tracking use. At first, Williams tubes—a storage system based on cathode ray tubes—were used, but these devices were always temperamental and unreliable. “Several researchers in the late 1940s, including Jay Forrester, conceived the idea of using magnetic cores for computer memory, but Forrester received the principal patent for his invention of the co-incident core memory that enabled the 3D storage of information.[3]. William Papian of Project Whirlwind cited one of these efforts, Harvard's "Static Magnetic Delay Line," in an internal memo. The first Core memory of 32 x 32 x 16 bits was installed on Whirlwind in the summer of 1953. Papian, described: "Magnetic-Core Storage has two big advantages: (1) greater reliability with a consequent reduction in maintenance time devoted to storage; (2) shorter access time (core access time is 9 microseconds: tube access time is approximately 25 microseconds) thus increasing the speed of computer operation.”[4] In April 2011, Forrester recalled that “the Wang use of cores did not have any influence on my development of random-access memory. The Wang memory was expensive and complicated. As I recall, which may not be entirely correct, it used two cores per binary bit and was essentially a delay line that moved a bit forward. To the extent that I may have focused on it, the approach was not suitable for our purposes”. He describes the invention and associated events, in 1975.[5]. Forrester has since observed "“It took us about seven years to convince the industry that random-access magnetic-core memory was the solution to a missing link in computer technology,” Forrester later said. “Then we spent the following seven years in the patent courts convincing them that they had not all thought of it first. ”[6]

Two key inventions led to the development of magnetic core memory in 1951. The first, An Wang's, was the write-after-read cycle, which solved the problem of how to use a storage medium in which the act of reading erased the data read enabling the construction of a serial, one dimensional shift register of o(50) bits, using two cores to store a bit. A Wang core shift register is in the Revolution exhibit at the Computer History Museum. The second, Jay Forrester's, was the coincident-current system, which enabled a small number of wires to control a large number of cores enabling 3D memory arrays of several million bits e.g. 8K x 8K x 64 bits.

Project Whirlwind core memory, circa 1951

Forrester's coincident-current system required one of the wires to be run at 45 degrees to the cores, which proved impossible to wire by machine, so that core arrays had to be assembled under microscopes by workers with fine motor control. Initially, garment workers were used. Successful automated assembly was only achieved in the 1970s around the time core memory became obsolete; because of this, automated assembly never entered the actual industrial production of core memory.

It was during the early 1950s that Seeburg developed the use of this coincident current ferrite core memory storage in the "Tormat" memory of its new range of jukeboxes, starting with the V200 released in 1955. Development work was completed in 1953.

By the late 1950s industrial plants had been set up in the Far East to build core. Inside, hundreds of workers strung cores for low pay. This lowered the cost of core to the point where it became largely universal as main memory by the early 1960s, replacing both inexpensive low-performance drum memory and costly high-performance systems using vacuum tubes, and later transistors, as memory. Some manufacturers also employed Scandinavian seamstresses who had been laid off due to mechanization of the textile industry.

The cost of core memory declined sharply over the lifetime of the technology: costs began at roughly US$1.00 per bit and dropped to roughly US$0.01 per bit. Core was replaced by integrated semiconductor RAM chips in the 1970s.

Wang's patent was not granted until 1955, and by that time core was already in use. This started a long series of lawsuits, which eventually ended when IBM bought the patent outright from Wang for US$500,000.[7] Wang used the funds to greatly expand Wang Laboratories, which he had co-founded with Dr. Ge-Yao Chu, a school mate from China. In 1964, after years of legal wrangling, IBM paid MIT $13 million for rights to Forrester’s patent—the largest patent settlement to that date.[8]

Core memory was part of a family of related technologies, now largely forgotten, which exploited the magnetic properties of materials to perform switching and amplification. By the 1950s vacuum-tube electronics was well-developed and very sophisticated, but tubes had a limited lifetime, used much more power and were much larger than semiconductor or magnetic technology, and their operating characteristics changed over their life. Magnetic devices had many of the virtues of the discrete and integrated solid-state devices that would replace them, and were extensively used in military applications. A notable example was the portable (truck-based) MOBIDIC computer developed by Sylvania for the United States Army Signal Corps in the late 1950s. The contents of electronic memory were lost when power was disconnected, but core memory was non-volatile and kept its contents.

Description

Diagram of a 4×4 plane of magnetic core memory in an X/Y line coincident-current setup. X and Y are drive lines, S is sense, Z is inhibit. Arrows indicate the direction of current for writing.

The term "core" comes from conventional transformers whose windings surround a magnetic core. In core memory the wires pass once through any given core—they are single-turn devices. The magnetic material for a core memory requires a high degree of magnetic remanance, the ability to stay highly magnetized, and a low coercitivity so that less energy is required to change the magnetization direction. The core can take two states, encoding one bit, which can be read when "selected" by a "sense wire". The core memory contents are retained even when the memory system is powered down (non-volatile memory). However, when the core is read, it is reset to a "zero" which is known as destructive readout. Circuits in the computer memory system then restore the information in an immediate re-write cycle. The properties of materials used for memory cores are dramatically different from those used in power transformers.

How core memory works

The most common form of core memory, X/Y line coincident-current – used for the main memory of a computer, consists of a large number of small ferrite (ferromagnetic ceramic) toroids — cores— held together in a grid structure (each grid called a plane), with wires woven through the holes in the cores' middle. In early systems there were four wires, X, Y, Sense and Inhibit, but later cores combined the latter two wires into one Sense/Inhibit line. Each toroid stores one bit (a 0 or 1). One bit in each plane could be accessed in one cycle, so each machine word in an array of words was spread over a stack of planes. Each plane would manipulate one bit of a word in parallel, allowing the full word to be read or written in one cycle.

Core relies on the "square loop" properties of the ferrite material used to make the toroids. Wires that pass through the cores create magnetic fields. Only a magnetic field greater than a certain intensity ("select") can cause the core to change its magnetic polarity. To select a memory location, one of the X and one of the Y lines are driven with half the current ("half-select") required to cause this change. Only the combined magnetic field generated where the X and Y lines cross (a logical AND function) is sufficient to change the state; other cores will see only half the needed field ("half-selected"), or none at all. By driving the current through the wires in a particular direction, the resulting induced field forces the selected core's magnetic flux to circulate in one direction or the other (clockwise or counterclockwise). One direction is a stored 1, while the other is a stored 0.

Close-up of core plane shown at top. The distance between the rings is roughly 1 mm (0.04 in). The green horizontal wires are X; the Y wires are dull brown and vertical, toward the back. The sense wires are diagonal, colored orange, and the inhibit wires are vertical twisted pairs.

The toroidal shape of a core is preferred since the magnetic path is closed, there are no magnetic poles and thus very little external flux. This allows the cores to be packed closely together and to not have their magnetic fields interact. The alternating 45 degree positioning in a core array helps to reduce any stray coupling.

Reading and writing

Reading from core memory is somewhat complex. Basically the read operation consists of doing a "flip to 0" operation to the bit in question, that is, driving the selected X and Y lines in the direction that causes the core to flip to whatever polarity the machine considers to be zero. If the core was already in the 0 state, nothing will happen. However if the core was in the 1 state it will flip to 0. If this flip occurs, after a brief delay, a voltage pulse is induced into the Sense line, saying, in effect, that the memory location used to hold a 1. If the pulse is not seen, that means no flip occurred, so the core must have already been in the 0 state. Note that every read forces the core in question into the 0 state, so reading is destructive, which is one of the attributes of core memory. The delay in sensing the voltage pulse is called the "access time" of the core memory.

Diagram of the hysteresis curve for a magnetic memory core during a read operation. Sense line current pulse is high ("1") or low ("0") depending on original magnetization state of the core.

Writing is similar in concept, but always consists of a "flip to 1" operation, relying on the memory already having been set to the 0 state in a previous read. For the write operation, the current in the X and Y lines goes in the opposite direction as it did for the read operation. If the core in question is to hold a 1, then the operation proceeds normally and the core flips to 1. However if the core is to instead hold a zero, the same amount of current as is used on the X and Y lines is also sent into the Inhibit line, which drops the combined field from the X, Y and Inhibit lines to half of the field needed to flip the core magnetization state. This leaves the core in the 0 state. The "access time" plus the time to rewrite is called the memory "cycle time".

Note that the Sense and Inhibit wires are used one after the other, never at the same time. For this reason later core systems combined the two into a single wire, and used circuitry in the memory controller to switch the duty of the wire from Sense to Inhibit.

A fundamental principle of core memory is that each read must be followed immediately by a write, to restore the value that is always destroyed by the read operation. Many computers began to include instructions that took advantage of this fact; if a location was going to be read, changed and re-written (for example by an increment operation), the computer would ask the memory controller to do the read, but then signal it to pause before doing the write that would normally follow. Once the increment instruction was complete the controller would be unpaused, and the usual write would occur, but using the new value. For certain types of operations, this effectively doubled the performance.

Other forms of core memory

A 10.8×10.8 cm plane of magnetic core memory with 64 x 64 bits (4 Kib), as used in a CDC 6600. Inset shows word line architecture with 2 wires per bit

Word line core memory was often used to provide register memory. Other names for this type are linear select and 2-D. This form of core memory typically wove three wires through each core on the plane, word read, word write, and bit sense/write. To read or clear words, the full current is applied to one or more word read lines; this clears the selected cores and any that flip induce voltage pulses in their bit sense/write lines. For read, normally only one word read line would be selected; but for clear, multiple word read lines could be selected while the bit sense/write lines ignored. To write words, the half current is applied to one or more word write lines, and half current is applied to each bit sense/write line for a bit to be set. In some designs, the word read and word write lines were combined into a single wire, resulting in a memory array with just two wires per bit. For write, multiple word write lines could be selected. This offered a performance advantage over X/Y line coincident-current in that multiple words could be cleared or written with the same value in a single cycle. A typical machine's register set usually used only one small plane of this form of core memory. Some very large memories were built with this technology, for example the Extended Core Storage (ECS) auxiliary memory in the CDC 6600, which was up to 2 million 60-bit words.

Another form of core memory called core rope memory provided read-only storage. In this case, the cores, which had more linear magnetic materials, were simply used as transformers; no information was actually stored magnetically within the individual cores. Each bit of the word had one core. Reading the contents of a given memory address generated a pulse of current in a wire corresponding to that address. Each address wire was threaded either though a core to signify a binary [1], or around the outside of that core, to signify a binary [0]. As expected, the cores were much larger physically than those of read-write core memory. This type of memory was exceptionally reliable. An example was the Apollo Guidance Computer used for the moon landings.

Physical characteristics

The performance of early core memories can be characterized in today's terms as being very roughly comparable to a clock rate of 1 MHz (equivalent to early 1980s home computers, like the Apple II and Commodore 64). Early core memory systems had cycle times of about 6 µs, which had fallen to 1.2 µs by the early 1970s, and by the mid-70s it was down to 600 ns (0.6 µs). Some designs had substantially higher performance: the CDC 6600 had a memory cycle time of 1.0 µs in 1964, using cores that required a half-select current of 200 mA.[9] Everything possible was done in order to decrease access times and increase data rates (bandwidth), including the simultaneous use of multiple grids of core, each storing one bit of a data word. For instance a machine might use 32 grids of core with a single bit of the 32-bit word in each one, and the controller could access the entire 32-bit word in a single read/write cycle.

Core memory is non-volatile storage – it can retain its contents indefinitely without power. It is also relatively unaffected by EMP and radiation. These were important advantages for some applications like first generation industrial programmable controllers, military installations and vehicles like fighter aircraft, as well as spacecraft, and led to core being used for a number of years after availability of semiconductor MOS memory (see also MOSFET). For example, the Space Shuttle flight computers initially used core memory, which preserved the contents of memory even through the Challenger's explosion and subsequent plunge into the sea in 1986.[citation needed]

Another characteristic of early core was that the coercive force was very temperature sensitive: the proper half select current at one temperature is not the proper half select current at another temperature. So the memory controllers would include temperature sensors (typically a thermistor) to adjust the current levels correctly for temperature changes. An example of this is the core memory used by Digital Equipment Corporation for their PDP-1 computer; this strategy continued through all of the follow-on core memory systems built by DEC for their PDP line of air-cooled computers. Another method of handling the temperature sensitivity was to enclose the magnetic core "stack" in a temperature controlled oven. Examples of this are the heated air core memory of the IBM 1620 (which could take up to 30 minutes to reach operating temperature, about 106 °F, 41 °C) and the heated oil bath core memory of the IBM 7090, early IBM 7094s, and IBM 7030.

Core was heated instead of cooled because the primary requirement was a consistent temperature, and it was easier (and cheaper) to maintain a constant temperature well above room temperature than one at or below it.

In 1980, the price of a 16 kW (kiloword, equivalent to 32kB) core memory board that fitted into a DEC Q-bus computer was around US$3,000. At that time, core array and supporting electronics fit on a single printed circuit board about 25 x 20 cm in size, the core array was mounted a few mm above the PCB and was protected with a metal or plastic plate.

Diagnosing hardware problems in core memory required time-consuming diagnostic programs to be run. While a quick test checked if every bit could contain a one and a zero, these diagnostics tested the core memory with worst-case patterns and had to run for several hours. As most computers had just a single core memory board, these diagnostics also moved themselves around in memory, making it possible to test every bit. An advanced test was called a "Schmoo test" in which the half select currents were modified along with the time at which the sense line was tested ("strobed") It seems the data plot looked like a cartoon character called "Schmoo" and the name stuck. In many occasions, errors could be resolved by gently tapping the printed circuit board with the core array on a table. This slightly changed the position of the cores to the wires running through and could fix the problem. The procedure was seldom needed, as core memory proved to be very reliable compared to other computer components of the day.

See also

References

  1. ^ Edwin D. Reilly, "Milestones in computer science and information technology," Greenwood Press: Westport, CT, 2003, p. 164, ISBN 1573565210
  2. ^ Wang Interview, An Wang's Early Work in Core Memories, Datamation, 1976, March, ppp. 161-163
  3. ^ Jay w. Forrester, Digital Information In Three Dimensions Using Magnetic Cores, Journal of Applied Physics 22, 1951
  4. ^ Whirlwind, p13. [1]
  5. ^ Jay W. Forrester Interview by Christopher Evans, Annals of the History of Computing, Volume 5, Number 3, July 1983, p 297-301
  6. ^ "excerpt of The Age of Heretics: A History of Radical Thinkers Who Reinvented Corporate Management, by Art Kleiner". The MIT Sloan Review. http://sloanreview.mit.edu/feature/jay-forrester-shock-to-the-system/. Retrieved 2008. 
  7. ^ "An Wang Sells Core Memory Patent to IBM". Computer History Museum. http://www.computerhistory.org/tdih/March/4/. Retrieved 2010-04-12. 
  8. ^ http://www.computerhistory.org/revolution/memory-storage/8/253
  9. ^ Control Data 6600 Training Manual, section 4, June 1965, document number 60147400

Patents

  • U.S. Patent 2,667,542 "Electric connecting device" (matrix switch with iron cores that operate as a cross-point switch. A series of X analog or telephone signal inputs can be routed to Y outputs.), filed September 1951, issued January 1954
  • U.S. Patent 2,708,722 "Pulse transfer controlling devices," An Wang filed October 1949, issued May 1955
  • U.S. Patent 2,736,880 "Multicoordinate digital information storage device" (coincident-current system), Jay Forrester filed May 1951, issued February 28, 1956
  • U.S. Patent 2,970,291 “Electronic Relay Circuit” (The patent notes “My invention relates to electric circuits employing relays…”) filed May 28, 1947, issued January 31, 1961.
  • U.S. Patent 2,992,414 “Memory Transformer” (The patent notes that “My invention relates to electric relay circuits and more particularly to improved transformers for use therein.”) filed May 29, 1947, issued July 11, 1961.
  • U.S. Patent 3,161,861 "Magnetic core memory" (improvements) Ken Olsen filed November 1959, issued December 1964
  • 713 U.S. Patent 3,264m 713 “Method of Making Memory Core Structures” (The patent notes “This invention relates to magnetic memory devices, and more particularly to a new and improved memory core structure and method of making the same…”) filed January 30, 1962, issued August 9, 1966.
  • U.S. Patent 3,421,152 "Linear select magnetic memory system and controls therefor," W. J. Mahoney, issued January 7, 1969
  • U.S. Patent 4,161,037 "Ferrite core memory" (automated production), July 1979
  • U.S. Patent 4,464,752 "Multiple event hardened core memory" (radiation protection), August, 1984

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