High-level synthesis

High-level synthesis

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior.[1] The starting point of a high-level synthesis flow is ANSI C/C++/SystemC code. The code is analyzed, architecturally constrained, and scheduled to create a register transfer level hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process.[2]

Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.[3] The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.



Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the FSM. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexors, registers and wires of the data path.

First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler[4] and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.[5]

In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behaviorial synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification.[6] Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.

High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.[7]

Source Input

The most common source inputs for high level synthesis are based on standards languages such as ANSI C/C++ and SystemC.

High level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with a FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete.[8]

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.[9]

  • Lexical processing
  • Algorithm optimization
  • Control/Dataflow analysis
  • Library processing
  • Resource allocation
  • Scheduling
  • Functional unit binding
  • Register binding
  • Output processing
  • Input Rebundling


Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis.[2] These constraints can be broken into

  • Hierarchy
  • Interface
  • Memory
  • Loop
  • Low-level timing constraints
  • iteration

Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.[10]

See also



  1. ^ Springer Book High Level Synthesis From Algorithm to Digital Circuit ISBN 978-1-4020-8587-1
  2. ^ a b EETimes The 'why' and 'what' of algorithmic synthesis
  3. ^ UBS University, France C-Based Rapid Prototyping for Digital Signal Processing
  4. ^ BDTI Architectural Design Of DSP ASICs: Tools And Techniques
  5. ^ EETimes Behavioral synthesis crossroad
  6. ^ EETimes: High-level synthesis rollouts enable ESL
  7. ^ SCDSource 2008 ESL goes mainstream with synthesis, virtual platforms
  8. ^ Multiple Word-Length High-Level Synthesis EURASIP Journal on Embedded Systems
  9. ^ A look inside behavioral synthesis, EETimes 2004
  10. ^ DesignCon Design Space Exploration for high performance signal processing hardware using ESL design metholodologies

Further reading

  • Coussy, P.; Gajski, D. D.; Meredith, M.; Takach, A. (2009). "An Introduction to High-Level Synthesis". IEEE Design & Test of Computers 26 (4): 8–17. doi:10.1109/MDT.2009.69.  edit
  • Alice C. Parker, Yosef Tirat-Gefen, Suhrid A. Wadekar (2007). "System-Level Design". In Wai-Kai Chen. The VLSI handbook (2nd ed.). CRC Press. ISBN 9780849341991. chapter 76. 
  • Shahrzad Mirkhani, Zainalabedin Navabi (2007). "System Level Design Languages". In Wai-Kai Chen. The VLSI handbook (2nd ed.). CRC Press. ISBN 9780849341991. chapter 86.  covers the use of C/C++, SystemC, TML and even UML
  • John P. Elliott (1999). Understanding behavioral synthesis: a practical guide to high-level design. Springer. ISBN 9780792385424. 
  • Liming Xiu (2007). VLSI circuit design methodology demystified: a conceptual taxonomy. Wiley-IEEE. ISBN 9780470127421. 
  • Ewout S. J. Martens; Georges Gielen (2008). High-level modeling and synthesis of analog integrated systems. Springer. ISBN 9781402068010. 
  • Michael Fingeroff (2010). High-Level Synthesis Blue Book. Xlibris Corporation. ISBN 9781450097246. 

External links

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