Rock (processor)

Infobox Computer Hardware Cpu
name = Rock


produced-start =
produced-end =
slowest = 2.3 | slow-unit = GHz
fastest =
arch = SPARC V9
numcores = 16

Rock is a multithreading, multicore, SPARC-family microprocessor currently in development at Sun Microsystems. It is a separate development from the Niagara (UltraSPARC T1 and T2) family.

Rock aims at higher per-thread performance, higher floating-point performance, and greater SMP scalability than the Niagara family. The Rock processor targets traditional high-end data-facing workloads, such as back-end database servers, as well as floating-point intensive high-performance computing workloads, whereas the Niagara family targets network-facing workloads such as web servers.

Sun expects to ship Rock processor based servers in 2009. [ [http://www.theregister.co.uk/2007/12/14/sun_rock_delays/ Sun's Rock chip waves goodbye to 2008 ship date | The Register ] ]

Processor core

The Rock processor implements the SPARC V9 64-bit instruction set, plus the VIS 3.0 SIMD multimedia instruction set extension. [cite web
url = http://sun.com/processors/vis/download/mlib/mlib_wp.pdf
title = MT mediaLib for Chip MultiThreaded (CMT) Processors
accessdate = 2007-12-03
author = Liang He
coauthors = Harlan McGhan
month = May | year = 2005
publisher = Sun Microsystems, Inc.
format=PDF
] Each Rock processor chip includes sixteen cores, with each core capable of running two threads simultaneously, yielding 32 threads per chip. The 16 cores are arranged in 4 "core clusters". Servers built with Rock will use FB-DIMMs which can be used to increase reliability, speed and density of memory systems. The Rock processor is planned for a 65nm manufacturing process and the design frequency is 2.3 GHz. [cite web|first=Brian|last=Neal|url=http://www.aceshardware.com/read.jsp?id=55000245|title=Architecting the Future: Dr. Marc Tremblay|date=March 24, 2003|publisher=Ace's Hardware]

Core cluster

The 16 cores in Rock are arranged in 4 "core clusters". Cores in a cluster share an 32KB instruction cache, two 32KB data caches, and two floating point units. Sun designed the chip this way because server workloads usually have high re-utilization in data and instruction across processes and threads but low number of floating-pointing operations in general. Thus sharing hardware resources among the 4 cores in a cluster leads to significant savings in area and power but low impact to performance. [cite web|url=http://www.opensparc.net/pubs/preszo/08/RockISSCC08.pdf|title=A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor|date=2008-02-13|publisher=Sun Microsystems|format=PDF]

Unconventional features

Sun has publicly disclosed a feature in the Rock processor called "hardware scout". Hardware scout uses otherwise idle chip execution resources to perform prefetching during cache misses. [cite journal|url=http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/2005/03/m3toc.xml&DOI=10.1109/MM.2005.49|first=S.|last=Chaudhry|coauthors=S. Yip; P. Caprioli; M. Tremblay|title=High Performance Throughput Computing|journal=IEEE Micro|volume=25|issue=3|year=2005|doi=10.1109/MM.2005.49]

In March 2006, Marc Tremblay, Vice President and Chief Architect for Sun's Scalable Systems Group, gave a presentation at the Xerox Palo Alto Research Center (PARC) on thread-level parallelism, hardware scouting, and thread-level speculation. [cite conference|url=http://www.parc.xerox.com/cms/get_article.php?id=530|first=M.|last=Tremblay|authorlink=Marc Tremblay|title=High Performance Throughput Computing|booktitle=PARC Forum|location=Palo Alto, CA|date=March 2, 2006] These multithreading technologies are expected to be included in the Rock processor.

In August 2007, Sun confirmed that Rock will be the first production processor to support transactional memory. [cite web|url=http://research.sun.com/spotlight/2007/2007-08-13_transactional_memory.html|title=Transactional Memory|date=2007-08-13|publisher=Sun Microsystems]

Sun engineers will be presenting the transactional memory interface at "Transact 2008", and the "Adaptive Transactional Memory Test Platform" simulator will be available to the general public in the short term. [cite web|url=http://blogs.sun.com/dave/resource/transact08-dice.pdf|title=Applications of the Adaptive Transactional Memory Test Platform|date=2008-02-13|publisher=Sun Microsystems|format=PDF] [cite web|url=http://blogs.sun.com/HPC/entry/video_transactional_memory_on_rock|title=Rock's Transactional Memory|date=2008-04-25|publisher=Sun Microsystems]

First silicon

In Jan 2007, Sun announced the tape-out of Rock. [cite web|url=http://www.sun.com/aboutsun/pr/2007-01/sunflash.20070118.3.xml|title=Sun Expands Solaris/SPARC CMT Innovation Leadership|date=2007-01-18|publisher=Sun Microsystems] In April 2007, Sun CEO Jonathan I. Schwartz blogged an image of a fabricated and BGA-packaged Rock chip, labeled UltraSPARC RK, and disclosed that it can address 256 terabytes of virtual memory in a single system running Solaris. [cite web|url=http://blogs.sun.com/jonathan/entry/rock_arrived|title=Rock Arrived|date=2007-04-10|publisher=Sun Microsystems]

In May 2007, Sun announced the first silicon of Rock booting Solaris successfully. [cite web|url=http://www.sun.com/aboutsun/pr/2007-05/sunflash.20070502.1.xml|title=Sun Microelectronics Hits Key Milestone in High-End UltraSPARC Development|date=2007-05-02|publisher=Sun Microsystems]

As a result of the ISSCC more information is coming out. Here is a new article based on this information: "Can you smell what the Rock is cookin'?" [cite web|url=http://arstechnica.com/news.ars/post/20080204-sun-can-you-smell-what-the-rock-is-cookin.html|title=Sun: Can you smell what the Rock is cookin'?|date=2008-02-04|publisher=Arstechnica]

References


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